R2J20602NP#13 Renesas Electronics America, R2J20602NP#13 Datasheet - Page 11
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R2J20602NP#13
Manufacturer Part Number
R2J20602NP#13
Description
IC MOSFET DRVR 12V 40A 56-QFN
Manufacturer
Renesas Electronics America
Type
High Side/Low Side Driverr
Datasheet
1.R2J20602NP13.pdf
(15 pages)
Specifications of R2J20602NP#13
Input Type
Non-Inverting
Number Of Outputs
2
Current - Peak Output
40A
Voltage - Supply
7 V ~ 7.8 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
On-state Resistance
-
Other names
Q4076981
R2J20602NP#13
R2J20602NP#13TR
R2J20602NP#13
R2J20602NP#13TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
R2J20602NP
The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route
from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function
operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has
been entered and GH and GL have become low, a PWM input voltage of 4.0 V or more is required to make the circuit
return to normal operation.
For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for
operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH
pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the
VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap
capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so
VBOOT is boosted to VSWH + 5 V.
The GH and GL pins are the gate-monitor pins for each MOS FET.
MOS FETs
The MOS FETs incorporated in R2J20602NP are highly suitable for synchronous-rectification buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
REJ03G1480-0200 Rev.2.00 Nov 30, 2007
Page 11 of 14
PWM
GH
GL
PWM
GH
GL
4.0 V
1.2 V
4.0 V
1.2 V
240 ns(t
240 ns(t
HOLD-OFF
HOLD-OFF
Figure 1
)
)
240 ns(t
240 ns(t
HOLD-OFF
HOLD-OFF
)
)