IRMCK371TR International Rectifier, IRMCK371TR Datasheet
IRMCK371TR
Specifications of IRMCK371TR
Available stocks
Related parts for IRMCK371TR
IRMCK371TR Summary of contents
Page 1
Sensorless Motor Control IC for Appliances Features TM MCE (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Support Induction motor sensorless FOC control Supports both interior and surface permanent ...
Page 2
... SPI Read AC Timing...................................................................................................22 7.9 UART AC Timing...............................................................................................................23 7.10 CAPTURE Input AC Timing ...........................................................................................24 7.11 JTAG AC Timing ............................................................................................................25 7.12 OTP Programming Timing .............................................................................................26 8 I/O Structure.............................................................................................................................27 9 Pin List .....................................................................................................................................30 10 Package Dimensions ............................................................................................................32 11 Part Marking Information ......................................................................................................33 12 Order Information .................................................................................................................33 www.irf.com TABLE OF CONTENTS 2 IRMCK371 © 2007 International Rectifier ...
Page 3
... Figure 22 Analog operational amplifier output and AREF I/O structure.......................................28 Figure 23 VPP programming pin I/O structure ..........................................................................28 Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................29 Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................29 Figure 26 XTAL0/XTAL1 pins structure .......................................................................................29 www.irf.com TABLE OF FIGURES 3 IRMCK371 © 2007 International Rectifier ...
Page 4
... Table 12. GATEKILL to SVPWM AC Timing ...............................................................................19 Table 13. Interrupt AC Timing......................................................................................................19 2 Table 14 Timing ..............................................................................................................20 Table 15. SPI Write AC Timing ....................................................................................................21 Table 16. SPI Read AC Timing....................................................................................................22 Table 17. UART AC Timing .........................................................................................................23 Table 18. CAPTURE AC Timing ..................................................................................................24 Table 19. JTAG AC Timing ..........................................................................................................25 Table 20. OTP Programming Timing ...........................................................................................26 Table 21. Pin List .........................................................................................................................31 www.irf.com TABLE OF TABLES 4 IRMCK371 © 2007 International Rectifier ...
Page 5
... Overview IRMCK371 is a new International Rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK371 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE ...
Page 6
... Motion Control Engine (MCE o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) www.irf.com IRMCK371 © 2007 International Rectifier ...
Page 7
... One channel of analog output (8-bit PWM) o UART C/SPI port o 64K byte program OTP o 2K byte data RAM. Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. www.irf.com Note 1 Note 1 7 IRMCK371 © 2007 International Rectifier ...
Page 8
... Pinout XTAL0 1 XTAL1 2 3 P1.0/T2 4 P1.1/RXD 5 P1.2/TXD 6 P1.3/SYNC/SCK 7 P1.4/CAP 8 VDD2 9 VSS 10 VDD1 11 P2.0/NMI P2.1 12 www.irf.com (Top View Figure 3. IRMCK371 Pin Configuration 8 IRMCK371 P3.0/INT2/CS1 35 PWMUH PWMUL 34 PWMVH 33 32 PWMVL 31 PWMWH 30 PWMWL 29 GATEKILL 28 VDD1 27 VSS 26 VDD2 25 AIN2 © 2007 International Rectifier ...
Page 9
... Figure 4. Input/Output of IRMCK371 9 IRMCK371 PWMUH PWMUL PWMVH PWM gate signal PWMVL Interface PWMWH PWMWL GATEKILL AVDD AVSS AREF CMEXT A/D Interface IFB+ IFB- IFBO AIN0 AIN1 AIN2 VDD1 Digital power/ VDD2 ground VSS PLL power/ PLLVDD ground PLLVSS © 2007 International Rectifier ...
Page 10
Peripheral Interface Group UART Interface P1.2/TXD Output, Transmit data from IRMCK371, can be configured as P1.2 P1.1/RXD Input, Receive data to IRMCK371, can be configured as P1.1 Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as ...
Page 11
... Must be tied to VSS, used only for factory testing. P5.1/TSM Input/output port 5.1, configured as JTAG port by default P5.2/TDO Input/output port 5.2, configured as JTAG port by default P5.3/TDI Input/output port 5.3, configured as JTAG port by default TCK Input, JTAG test clock www.irf.com © 2007 International Rectifier 11 IRMCK371 ...
Page 12
... Low Loss PWMVL PWMWH Space PWMWL Vector PWM GATEKILL 0.6V IFBC+ S/H IFBC- IFBCO AIN0 AIN1 Other analog input (0-1.2V) AIN2 AREF Optional External Voltage Reference (0.6V) CMEXT AVDD 1.8V AVSS © 2007 International Rectifier Motor DC bus shunt resistor DC bus voltage ...
Page 13
... Table 2. System Clock Frequency Power Consumption 1.8V 3.3V Total Power MCE Frequency (MHz) 13 IRMCK371 Max Condition 3.6 V Respect to VSS 1.98 V Respect to VSS 1.98 V Respect to AVSS 3.65 V Respect to VSS 85 ˚C 150 ˚C Max Unit 128 MHz 32 MHz 100 120 140 © 2007 International Rectifier ...
Page 14
... Typ 1. PLLVSS 0.8* V PLLVDD Table 4. PLL DC Characteristics 14 IRMCK371 Max Condition 3.6 V Recommended 1.98 V Recommended 0.8 V Recommended 3.6 V Recommended (1) - ±1 μ ( (1) Max Condition 1.92 V Recommended 0. 1.8 V PLLVDD (1) V PLLVDD 1.8 V PLLVDD PLLVDD (1) © 2007 International Rectifier ...
Page 15
... Table 7. AREF DC Characteristics 15 IRMCK371 Max Condition 1.89 V Recommended 1.8 V AVDD 1.2 V Recommended 1 1.8 V AVDD (1) - Requested 20 kΩ between IFBO and IFB- ( 0.6 V OUT ( 0.6 V OUT (1) Max Condition 1. 3.3 V DD1 1. 3.3 V DD1 - Max Condition 700 1.8 V AVDD (1) - (1) - © 2007 International Rectifier ...
Page 16
... MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec - Table 8. PLL AC Characteristics R = =10 Xtal 2 C =30PF 1 C =30PF 2 Figure 7 Crystal oscillator circuit 16 IRMCK371 Max Condition (1) 60 MHz (see figure below) (1) 128 MHz (1) - (1) - (1) - (1) 500 μsec © 2007 International Rectifier ...
Page 17
... Data guaranteed by design. www.irf.com Min Typ - - - - Voltage droop t SAMPLE T HOLD Min Typ - 10 V/μsec Ω - 400 ns 17 IRMCK371 Max Condition (1) 2.05 μsec 10 μsec Voltage droop ≤ 15 LSB (see figure below) S/H Voltage Max Condition - AVDD ( ( 1 AVDD ( © 2007 International Rectifier ...
Page 18
... SYNC to PWM output dSYNC3 delay time Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events www.irf.com t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 Min Typ - Table 11. SYNC AC Characteristics 18 IRMCK371 Max Unit - SYSCLK 100 SYSCLK 200 SYSCLK (1) 2 SYSCLK © 2007 International Rectifier ...
Page 19
... Interrupt AC Timing Unless specified 25˚C. Symbol Parameter t INT0, INT1 Interrupt wINT Assertion Time t INT0, INT1 latency dINT www.irf.com Min Typ Figure 11 Interrupt AC Timing Min Typ Table 13. Interrupt AC Timing 19 IRMCK371 Max Unit - SYSCLK 100 SYSCLK Max Unit - SYSCLK 4 SYSCLK © 2007 International Rectifier ...
Page 20
... C read setup time is determined by the programmable filter time applied to I communication. www.irf.com T T I2CLK I2CLK I2WSETUP I2WHOLD I2RSETUP 2 Figure Timing Min Typ 10 0.25 0.25 0.25 0. filter time 1 2 Table 14 Timing 20 IRMCK371 t I2EN1 t I2RHOLD t I2EN2 Max Unit - 8192 SYSCLK - - T I2CLK - - T I2CLK - - T I2CLK - - T I2CLK - - SYSCLK - - SYSCLK 2 C © 2007 International Rectifier ...
Page 21
... CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 13 SPI write AC Timing Min Typ 1 Table 15. SPI Write AC Timing 21 IRMCK371 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec 10 nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
Page 22
... RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 14 SPI read AC Timing Min Typ 1 Table 16. SPI Read AC Timing 22 IRMCK371 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec - nsec - nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
Page 23
... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD www.irf.com Data and Parity Bit Stop Bit T UARTFIL Figure 15 UART AC Timing Min Typ - 57600 - 1/16 Table 17. UART AC Timing 23 IRMCK371 Max Unit - bit/sec - T BAUD © 2007 International Rectifier ...
Page 24
... CAPTURE rising edge CLDELAY to capture register latch time t CAPTURE input INTDELAY interrupt latency time www.irf.com Figure 16 CAPTURE Input AC Timing Min Typ Table 18. CAPTURE AC Timing 24 IRMCK371 Max Unit - SYSCLK - SYSCLK - SYSCLK 4 SYSCLK 4 SYSCLK 4 SYSCLK © 2007 International Rectifier ...
Page 25
... JHIGH t TCK Low Period JLOW t TCK to TDO propagation CO delay time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD www.irf.com t JHOLD Figure 17 JTAG AC Timing Min - Table 19. JTAG AC Timing 25 IRMCK371 Typ Max Unit - 50 MHz - - nsec - - nsec - 5 nsec - - nsec - - nsec © 2007 International Rectifier ...
Page 26
OTP Programming Timing Figure 18 OTP Programming Timing Unless specified 25˚C. Symbol Parameter T VPP Setup Time VPS T VPP Hold Time VPH Rev 1.0 Min 10 15 Table 20. OTP Programming Timing Typ Max Unit - ...
Page 27
... Figure 19 All digital I/O except motor PWM output The following figure shows RESET and GATEKILL I/O structure. www.irf.com VDD1 (3.3V) 70k Low true logic 6.0V 100 6.0V VSS VDD1 (3.3V) RESET GATEKILL I/O 6.0V PIN 100 6.0V VSS Figure 20 RESET, GATEKILL I/O 27 IRMCK371 70k © 2007 International Rectifier ...
Page 28
... Figure 23 VPP programming pin I/O structure www.irf.com AVDD Analog input 6.0V PIN 100 Analog Circuit 6.0V AVSS Figure 21 Analog input 1.8V Analog output 6.0V PIN Analog Circuit 6.0V AVSS VPP input PIN 100 Analog Circuit 8.0V VSS 28 IRMCK371 © 2007 International Rectifier ...
Page 29
The following figure shows the VSS, AVSS and PLLVSS pin structure Figure 24 VSS, AVSS and PLLVSS pin structure The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...
Page 30
... PWM shutdown input, 2-μsec digital filter, configurable either high or low true. 70 kΩ Pull O PWM gate drive for phase W low side, configurable up either high or low true 70 kΩ Pull O PWM gate drive for phase W high side, up configurable either high or low true 30 IRMCK371 © 2007 International Rectifier ...
Page 31
... I/O Discrete I/O or JTAG test data input I JTAG test clock input 58 kΩ pull I Test mode input, must be tied to VSS down I/O Reset, low true, Schmitt trigger input P 1.8V PLL power P PLL ground Table 21. Pin List 31 IRMCK371 © 2007 International Rectifier ...
Page 32
... Package Dimensions www.irf.com © 2007 International Rectifier 32 IRMCK371 ...
Page 33
... Part Marking Information 12 Order Information Lead-Free Part in 48-lead QFP Moisture Sensitivity Rating – MSL3 Part number Order quantities IRMCK371TR 2000 parts on tape and reel in dry pack IRMCK371TY 2500 parts on trays (160 parts per tray) in dry pack www.irf.com www.irf.com This product has been designed and qualified for the industrial level Qualification standards can be found at IR WORLD HEADQUARTERS: 233 Kansas St ...