AMIS30512C5122G ON Semiconductor, AMIS30512C5122G Datasheet - Page 20

• Manufacturer Part Number: AMIS30512C5122G
• Description: IC MOTOR DVR MICRO STEP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of AMIS30512C5122G

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 6 V ~ 30 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Operating Temperature Classification: Automotive
• Package Type: SOIC
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Compliant

NOTE:
programmable through the WDT [3:0] bits (Table 12: SPI
Control Register WR). The timing is given in Table 11.
Table 11. Watchdog Timeout Interval as Function of
WDT[3.0]
The duration of the watchdog timeout interval is
Index
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
t
DSPI
is the time needed by the external microcontroller to shift-in the <WDEN> bit after a power-up.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WDT[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
t
WDTO
V
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VDD
DDH
VBB
t
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
POR/WD pin
Enable WD
Acknowledge WD
WD timer
t
WDTO
Figure 15. Watchdog Timing Diagram
> t
t
PU
WDPR
128
160
192
224
256
288
320
352
384
416
448
480
512
32
64
96
(ms)
t
or < t
POR
http://onsemi.com
t
WDTO
DSPI
20
CLR pin (=Hard Reset)
To reset the complete digital inside AMIS−30512, the input
CLR needs to be pulled to logic 1 during minimum time
given by T
clears all internal registers without the need of a
power−cycle. The operation of all analog circuits is
depending on the reset state of the digital, charge pump
remains active. Logic 0 on CLR pin resumes normal
operation again.
Sleep Mode
provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
•
•
•
•
•
•
•
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time t
to stabilize. After this time, NXT commands can be issued.
= t
Logic 0 on CLR pin allows normal operation of the chip.
The bit <SLP> in Table 15: SPI Control Register 2 is
The drivers are put in HiZ
All analog circuits are disabled and in low−power mode
All internal registers are maintaining their logic content
Pulses on NXT and DIR inputs are ignored
SPI communication remains possible (slight current
increase during SPI communication)
Reset of chip is possible through CLR pin
Oscillator and digital clocks are silent, except during
SPI communication
WDPR
t
WDRD
or = t
CLR
. (Table 5: AC Parameters) This reset function
WDTO
t
CPU
POR
is needed for the charge pump
t
t
t