LTC4355IS#TRPBF Linear Technology, LTC4355IS#TRPBF Datasheet - Page 9

• Manufacturer Part Number: LTC4355IS#TRPBF
• Description: IC IDEAL DIODE-OR 16-SOIC
• Manufacturer: Linear Technology

Specifications of LTC4355IS#TRPBF

• Applications: -48V Dist Power Systems, AdvancedTCA ® Systems
• Fet Type: N-Channel
• Number Of Outputs: 2
• Internal Switch(s): No
• Delay Time - Off: 300ns
• Voltage - Supply: 9 V ~ 80 V
• Current - Supply: 2mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - On: -

APPLICATIONS INFORMATION
System Power Supply Failure
The LTC4355 automatically supplies load current from the
system input supply with the higher voltage. If this supply
shorts to ground, reverse current begins to fl ow through
the pass transistor temporarily and the transistor begins
to turn off. When this reverse current creates –25mV of
voltage drop across the drain and source pins of the pass
transistor, a fast pull-down circuit engages to drive the
gate low faster.
The remaining system power supply delivers the load cur-
rent through the body diode of its pass transistor until the
channel turns on. The LTC4355 ramps the gate up with
20μA, turning on the N-channel MOSFET to reduce the
voltage drop across it.
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by para-
sitic resistances and inductances. During the reverse re-
covery phase, energy stored in the parasitic inductances
is transferred to other elements in the circuit. Current
slew rates during reverse recovery may reach 100A/μs
or higher.
SHORT
INPUT
Figure 1. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pins.
The Polarity of Step Recovery Spikes Is Shown Across Parasitic Inductances
V
V
IN1
IN2
INPUT PARASITIC
INPUT PARASITIC
INDUCTANCE
INDUCTANCE
SBR1U150SA
SBR1U150SA
+
–
D
D
IN1
IN2
–
+
IN1
FDS3672
GATE1
REVERSE RECOVERY CURRENT
M1
LTC4355
IN2
GND
RECOVERY
CURRENT
REVERSE
FDS3672
GATE2
M2
High slew rates coupled with parasitic inductances in se-
ries with the input and output paths may cause potentially
destructive transients to appear at the IN and OUT pins of
the LTC4355 during reverse recovery. A zero impedance
short-circuit directly across an input that is supplying
current is especially troublesome because it permits the
highest possible reverse current to build up during the
delay phase. When the MOSFET fi nally commutates the
reverse current the LTC4355 IN pin experiences a nega-
tive voltage spike, while the OUT pin spikes in the positive
direction.
To prevent damage to the LTC4355 under conditions of
input short-circuit, protect the IN pins and OUT pin as
shown in Figure 1. The IN pins are protected by clamping
to the GND pin in the negative direction. Protect the OUT
pin with a clamp, such as with a TVS or TransZorb, or with
a local bypass capacitor of at least 10μF. In low voltage
applications the MOSFET’s drain-source breakdown may
be suffi cient to protect the OUT pin, provided BV
V
Parasitic inductance between the load bypass or the
second supply and the LTC4355 allows a zero impedance
input short to collapse the voltage at the OUT pin, which
increases the total turn-off time (t
up to 30V, bypass the OUT pin with 39μF; above 30V use
at least 100μF. One capacitor serves to guard against OUT
collapse and also protect OUT from voltage spikes.
IN
OUT
< 100V.
4355 F01
C
10μF
OUT
OR
OUTPUT PARASITIC
INDUCTANCE
+
D
SMAT70A
CLAMP
–
C
V
LOAD
OUT
OFF
). For applications
LTC4355
DSS
4355fe
9
+