IR5001STRPBF International Rectifier, IR5001STRPBF Datasheet
IR5001STRPBF
Specifications of IR5001STRPBF
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IR5001STRPBF Summary of contents
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... A B FET Check Pulse FET A Status -48V input A Fet B Status -48V input B PACKAGE / ORDERING INFORMATION LEADFREE PIN PART NUMBER COUNT PER TUBE PER REEL IR5001SPbF 8 IR5001STRPbF 8 Data Sheet No.PD60229 revB IR5001S & (PbF) IR5001 Vline Vout DC Vcc Gnd DC FETch INN FETst ...
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ABSOLUTE MAXIMUM RATINGS Vline Voltage Vcc Voltage Icc Current INN, INP Voltage FETch, FETst FETst Sink Current Junction Temperature Storage Temperature Range CAUTION: 1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This ...
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PARAMETERS SYMBOL Output Section High Level Output Voltage Low Level Output Voltage Vout LO Turn-On DelayTime Rise Time Turn-Off Delay Time Fall Time FETch and FETst I(FETch) FETch Sink Current FETch Output Delay Time FETch_pd FETch Threshold Vth(FETch) FETst Threshold ...
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BLOCK DIAGRAM 50K V 1 LINE Vcc 2 12V Shunt 5V Regulator 5V, V REF 1.25V Generator 70K INP 5 clamp 70K INN 6 clamp FETch 3 Figure 2 - Simplified block diagram of the IR5001. www.irf.com UVLO 9V 5V ...
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PARAMETER DEFINITION AND TIMING DIAGRAM V OUT (0,0) V HYST V OS Figure 3 - Input Comparator Offset (Vos ) and Hysteresis Voltage (Vhyst) Definition. 10ns 90mV 50mV INP INN t d(on) ...
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TYPICAL OPERATING CHARACTERISTICS 180 170 160 150 140 130 120 -40 - Temperature (°C) Figure 6 - Turn Off Delay vs. Junction Temperature 5.7 5.6 5.5 5.4 5.3 5.2 5.1 -40 - Temperature (°C) ...
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TYPICAL OPERATING CHARACTERISTICS 13 Top: 25°C 85°C 12.8 125°C Bottom: -40°C 12.6 12.4 12.2 12 11.8 11 Vline (V) Figure 12 - Vcc vs. Vline and Junction Temperature 1.4 1.2 1 0.8 0.6 0.4 0 ...
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DETAILED PIN DESCRIPTION Vline and Vcc Vline and Vcc are the input and output pins of the internal shunt regulator. The internal shunt regulator regulates the Vcc voltage at ~12V. The Vcc pin should always be by-passed with a ceramic ...
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ORing conducting and Vout of the IR5001S is high (FET current flows from source to drain), the current must reverse the direction before the IR5001S will switch the FET off. The asymmetrical offset voltage prevents potential ...
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APPLICATION INFORMATION The IR5001S is designed for multiple active ORing and reverse polarity protection applications with minimal number of external components. Examples of typical circuit connections are shown below. Negative Rail ORing/Reverse Polarity Protection A typical connection of the IR5001S ...
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In a well - designed Active ORing circuit, the Rds(on) of the Active ORing FET should generate between 50mV to 100mV of (INP – INN) voltage during normal, steady state operation. (The normal operation refers to current flowing from the ...
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Surface Mount, Narrow Body PIN NO 8-PIN SYMBOL MIN MAX A 4.80 4.98 1.27 BSC B C 0.53 REF D 0.36 0.46 E 3.81 3.99 F 1.52 1.72 G 0.10 0.25 ...