LTC3524EUF#PBF Linear Technology, LTC3524EUF#PBF Datasheet - Page 6

• Manufacturer Part Number: LTC3524EUF#PBF
• Description: IC TFT BIAS SUPPLY ADJ 24-QFN
• Manufacturer: Linear Technology

Specifications of LTC3524EUF#PBF

• Applications: LCD Display
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Operating Supply Voltage (typ): 3.3/5V
• Number Of Segments: 8
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 24
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

PIN FUNCTIONS
LCD BIAS PIN FUNCTIONS
LTC3524
V
LED Boost Converters. This pin must be locally bypassed
with a minimum of 2.2μF.
GND/Exposed Pad (Pin 25): Signal and Power Ground for
the LTC3524. Provide a short, direct PCB path between GND
ELCD (Pin 1): Enable Input for the LTC3524’s LCD Cir-
cuits. LCD bias supplies are actively discharged to GND
when ELCD is low through internal pull down devices. An
optional RC network on ELCD provides a slower ramp-up
of the LCD boost converter inductor current during start-
up (soft-start). Shutdown mode is activated by driving
ELCD, ELED1, and ELED2 low. Shutdown disables all IC
functions and reduces quiescent current from the battery
to less than 2μA.
FBVO (Pin 3): Feedback Pin for the V
ence voltage is 1.225V. Connect resistive divider tap here
with minimum trace area.
V
and Input to the Voltage Doubler (2X) Stage. Bypass
V
between 4.7 and 22μF.
SW1 (Pin 5): Synchronous Boost Switch. Connect a
4.7μH-15μH inductor between SW1 and V
trace lengths as short and wide as possible to reduce EMI
and voltage overshoot. If the inductor current falls to zero,
the PMOS synchronous rectifi er is turned off to prevent
reverse charging of the inductor and an internal switch
connects SW1 to V
C2
node. The charge pump doubler fl ying capacitor is con-
nected between C2
nate between GND and V
cycle while the charge pump is operating. Use a 0.1μF
X5R type ceramic capacitor for best results.
6
IN
OUT
OUT
–
V
(Pin 2): Common Input Supply for LCD Bias and White
(Pin 6): Charge pump doubler fl ying capacitor negative
OUT
with a low ESR, ESL ceramic capacitor (X5R type)
(Pin 4): Main Output of the LCD Boost Regulator
=
1 225 1
.
⎛
⎝ ⎜
+
IN
and C2
+
to reduce EMI.
R
R
OUT
2
1
⎞
⎠ ⎟
–
. The voltage on C2
at an approximate 50% duty
(
See Block Diagram
OUT
Switcher. Refer-
IN
. Keep PCB
–
will alter-
)
C2
tive node. The charge pump doubler fl ying capacitor is
connected between C2
alternate between V
duty cycle while the charge pump is operating. Use a 0.1μF
X5R type ceramic capacitor for best results.
V2x (Pin 8): Charge Pump Doubler Output and Input to
the Charge Pump Quadrupler. This output generates 2X
V
type ceramic capacitor. C2
and V2x connected to V
to generate VH or VN.
VN
Inverter. The charge pump inverter can generate a regu-
lated negative voltage up to the voltage applied to VN
Connect VN
to VH, external diodes and a capacitor are required for
sequencing (see the Applications Information section).
CN+ (Pin 10): Charge Pump Inverter Flying Capacitor
Positive Node. The charge pump inverter fl ying capacitor
is connected between CN
(see Typical Application fi gures). The voltage on CN
alternate between GND and VN
duty cycle while the inverting charge pump is operating. Use
a 0.1μF X5R type ceramic capacitor for best results.
NC (PIN 11): No Connect. This pin should be connected
to GND.
VN (Pin 12): Negative Charge Pump Converter Output.
VN can be regulated down to approximately –VN
depending on where VN
bypassed to GND with at 0.47μF or larger X5R type ce-
ramic capacitor.
and the (–) side of the boost (V
tors, and the (–) side of the charge pump outputs (V2x,
VH, VN) fi lter capacitors. PCB ground must be soldered
to the Exposed Pad for proper operation.
OUT
+
IN
(Pin 7): Charge pump doubler fl ying capacitor posi-
. V2x should be bypassed to GND with a 0.47μF X5R
(Pin 9): Positive Voltage Input for the Charge Pump
IN
to V
OUT
OUT
, V2x, or VH. If VN
+
and V2x at an approximate 50%
and C2
OUT
IN
+
+
and external Schottky diodes
is connected. VN should be
and C2
if the doubler is not needed
IN
–
OUT
. The voltage on C2
at an approximate 50%
–
, VLED) fi lter capaci-
should be left open
IN
is connected
IN
+
+
volts
will
will
3524f
IN
.