MCZ33800EK Freescale Semiconductor, MCZ33800EK Datasheet - Page 3

• Manufacturer Part Number: MCZ33800EK
• Description: IC ENGINE CTRL SW/DVR 54-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33800EK

• Applications: Automotive
• Current - Supply: 10mA
• Voltage - Supply: 5 V ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Product: Fan / Motor Controllers / Drivers
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. 33800 Pin Definitions
Analog Integrated Circuit Device Data
Freescale Semiconductor
Pin Number
1, 3, 5, 50,
2, 4, 6, 49,
A functional description of each pin can be found in the Functional Pin Description section beginning on
52, 54
51, 53
48
10
11
12
13
14
7
8
9
VSSNS456
VSSNS123
Pin Name
GD1-GD6
VDSNS1-
VDSNS6
LRFDBK
SCLK
CS
P1
P3
P5
SI
Pin Function
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
CCD2_GND
CCD2_OUT
CCD2_REC
CCD1_OUT
VSSNS456
VDSNS4
VDSNS5
VDSNS6
LRFDBK
RI_REF
Source Voltage Sense The VSSNS pins are used to monitor the source voltage of the external
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Drain Voltage Sense
SCLK
Gate Driver Output
GD4
GD5
GD6
Serial Clock Input
Load Resistance
Serial Input Data
CS
EN
P1
P3
P5
P7
Formal Name
SI
Chip Select
Input Three
Feedback
Input One
Input Five
Figure 3. 33800 Pin Connections
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
The VDSNS pin is used to monitor the drain voltage of the external
MOSFET.
The GD pin provides gate drive for an external MOSFET
MOSFETS.
The LRFDBK pin is an operational amplifier output.
The SI input pin is used to receive serial data from the MCU. The serial
input data is latched on the rising edge of SCLK, and the input data
transitions on the falling edge of SCLK.
The SCLK input pin is used to clock in and out the serial data on the SI
and SO Pins while being addressed by the CS.
The Chip Select input pin is an active low signal sent by the MCU to
indicate that the device is being addressed. This input requires CMOS
logic levels and has an internal active pull up current source.
Input control of OSS output 1. When configured via the SPI, P1 input may
be used to control OSS output 1 and output 2 in parallel.
Input control of OSS output 3. When configured via the SPI, P3 input may
be used to control OSS output 3 and output 4 in parallel.
Input control of OSS output 5. When configured via the SPI, P5 input may
be used to control OSS output 5 and output 6 in parallel.
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDSNS3
GD3
VDSNS2
GD2
VDSNS1
GD1
VSSNS123
REXT
PGND1
OUT1
PGND2
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
OUT8
DEFAULT
SO
VDD
VCAL
GND
VPWR
CCD1_GND
CCD1_REC
Definition
page
PIN CONNECTIONS
16.
33800
3