ZM7316G-65503-T1 POWER ONE, ZM7316G-65503-T1 Datasheet - Page 26
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ZM7316G-65503-T1
Manufacturer Part Number
ZM7316G-65503-T1
Description
IC DIGITAL PWR CONTROLLER 64QFN
Manufacturer
POWER ONE
Datasheet
1.ZM7304G-65501-B1.pdf
(33 pages)
Specifications of ZM7316G-65503-T1
Applications
Digital Power Controller
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
12mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Input
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The ACFAIL_N and RES_N inputs should be controlled with open collector devices. The propagation
delay between the external device pulling the input low and the DPM pulling down OK lines and
triggering the turn-off process is approximately 1ms.
10.6.2 Front End Enable
The FE_EN pin is dedicated to the control of a DC-DC Front End. The Front End is typically used to
convert the 48V into the intermediate bus voltage (IBV). If the DPM is powered from an auxiliary
source, not from the IBV, it can control the DC-DC Front End.
When FE_EN is internally pulled up to 3.3V, the Front End is enabled. The FE_EN output can provide
up to 5mA of current. When the FE_EN goes low, the Front End is disabled. The Front End can be
enabled and disabled via the GUI IBS Monitoring Window or directly via the I
commands.
The FE_EN pin should not be directly connected to the Enable pin of the DC-DC Front End. Typically,
the Enable pin is referenced to the primary side of the Front End that is isolated from the low voltage
secondary side. In addition, the Enable pin can be pulled up internally to a voltage potentially damaging
to the DPM FE_EN output. The best method is to interface the DPM with the Front End through an
optocoupler as shown in Figure 20. This configuration provides interface for negative logic front ends.
10.6.3 Crowbar
When the crowbar protection is enabled, the CB pin is internally pulled up to 3.3V for 1ms. It is capable
of supplying 5mA to turn on a crowbar circuit.
10.6.4 HRES_N
The HRES_N is an active low digital input. When it is pulled low, the DPM will perform full hardware
reset including processor, memory, and communication interface. The POL converters and auxiliary
devices will be turned off although sequencing and tracking during the turn-off are not guaranteed.
Communication with a host processor or GUI (if established) will be lost. When the input is released,
the DPM will first program all POL converters and then turn them on, if the Auto Turn-On is enabled.
Unlike all other I/O pins on the ZM7300 DPM, the HRES_N does not have an internal ESD protection
diode connected to VDD. Therefore, it is necessary to add the diode externally as shown in Figure 3.
ZD-00896 Rev. 5.1, 13-Jul-10
Figure 20. Interface Between DPM and DC-DC Front End
FE_EN
DPM
GND
www.power-one.com
3.3k
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ZM7300G Series Digital Power Manager
Enable
-VIN
Front End
2
C bus using specific
Page 26 of 33
Data Sheet