ADT7473ARQZ ON Semiconductor, ADT7473ARQZ Datasheet - Page 56

• Manufacturer Part Number: ADT7473ARQZ
• Description: IC REMOTE THERMAL CTRLR 16QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7473ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16. ADT7473/ADT7473−1 Registers
Table 17. Voltage Reading Registers (Power−On Default = 0x00)
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76 and Register 0x77)
2. If V
3. V
Addr
0x7A
0x7B
0x7C
0x7D
0x7E
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7F
0x80
Register Address
must be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read.
Both the extended resolution registers and the MSB registers are frozen.
CC
CCP
R/W
0x21
0x22
(Pin 3) is the supply voltage for the ADT7473/ADT7473−1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
LO (Bit 1 of the Dynamic T
Local Temp.
Timer Limit
Resolution
Resolution
Pulses per
Revolution
Register 2
Register 1
Register 2
Register 3
Register 5
Register 4
Register 1
Register 2
Register 3
Remote 1
Remote 2
Extended
Extended
Interrupt
Interrupt
THERM
Register
THERM
Register
Config.
Config.
Config.
Config.
Desc
Temp.
Temp.
Status
TACH
Offset
Offset
Offset
Timer
Mask
Mask
Test
Test
Test
1
2
Read−only
Read−only
R2 THERM
R/W
SHDN
TDM2
Bit 7
FAN4
OOL
TMR
LIMT
RES
DC4
RES
D2
7
7
7
MIN
Control Register 1, 0x36) is set, V
THERM
CONV
TDM2
Bit 6
FAN4
Local
TMR
LIMT
RES
DC3
RES
R2T
D1
6
6
6
Reflects the voltage measurement at the V
Reflects the voltage measurement at the V
THERM
LTMP
ATTN
FAN3
V
Bit 5
LIMT
BpAtt
TMR
V
DC2
F4P
R1
LT
CCP
5
5
5
CC
http://onsemi.com
Do not write to these registers
Do not write to these registers
Do not write to these registers
THERM_LATCH
THERM HYSTR
ADT7473: RES
ADT7473: RES
ADT7473−1:
ADT7473−1:
CONFIG
LTMP
Bit 4
FAN3
FAN3
TMR
LIMT
AVG
DC1
R1T
V
56
4
4
4
CC
CCP
(Note 1)
THERM
GPIOP
Full on
Detect
TDM1
can control the sleep state of the ADT7473/ADT7473−1.
Bit 3
FAN3
FAN2
FAST
FAN2
V
TMR
LIMT
Max/
RES
CCP
3
3
3
Description
CCP
CC
BOOST
THERM
GPIOD
Disable
Detect
TDM1
Bit 2
FAN2
FAN1
V
FAN2
LIMT
TMR
V
CCP
input on Pin 3 (8 MSB of reading). (Note 3)
2
2
2
CC
input on Pin 14 (8 MSB of reading). (Note 2)
THERM
Detect
FUNC
Bit 1
FAN1
FAN1
Offset
V
LIMT
Temp
TMR
PIN9
OVT
RES
RES
CCP
1
1
1
Presence
COMPL
ALERT
Enable
TWOS
ASRT/
TMRO
FUNC
FAN1
Bit 0
LIMT
PIN9
FAN
RES
RES
RES
RES
DT
0
0
0
7473:
fault
0X55
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x10
ADT
De-
Lock-
able
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
−
−
−
−
−
−
−