ADT7463ARQZ ON Semiconductor, ADT7463ARQZ Datasheet - Page 30

• Manufacturer Part Number: ADT7463ARQZ
• Description: IC REMOTE THERMAL CTRLR 24-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7463ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADT7463
PWM1 CONFIGURATION (REG. 0x5C)
<2:0> SPIN These bits control the start-up timeout for PWM1.
PWM2 CONFIGURATION (REG. 0x5D)
<2:0> SPIN These bits control the start-up timeout for PWM2.
PWM3 CONFIGURATION (REG. 0x5E)
<2:0> SPIN These bits control the start-up timeout for PWM3.
Disabling Fan Start-Up Timeout
Although fan start-up makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up times.
Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40)
disables the spin-up for two TACH pulses. Instead, the fan spins
up for the fixed time as selected in Registers 0x5C to 0x5E.
PWM Logic State
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
PWM2 Configuration (Reg. 0x5D)
<4> INV
PWM3 Configuration (Reg. 0x5E)
<4> INV
PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Registers 0x5F to 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
Rev. 4 | Page 30 of 52 | www.onsemi.com
–30–
PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61)
<2:0> FREQ 000 = 11.0 Hz
Fan Speed Control
The ADT7463 can control fan speed using two different modes.
The first is automatic fan speed control mode. In this mode, fan
speed is automatically varied with temperature and without CPU
intervention, once initial parameters are set up. The advantage of
this is in the case of the system hanging, the user is guaranteed
that the system is protected from overheating. The automatic fan
speed control incorporates a feature called dynamic T
tion. This feature reduces the design effort required to program
the automatic fan speed control loop. For more information and
how to program the automatic fan speed control loop and dynamic
T
Fan Speed Control Loop application note (www.analog.com/
UploadedFiles/Application_Notes/331085006AN613_0.pdf).
The second fan speed control method is manual fan speed control
which is described in the next paragraph.
Manual Fan Speed Control
The ADT7463 allows the duty cycle of any PWM output
to be manually adjusted. This can be useful if users wish to
change fan speed in software or want to adjust PWM duty cycle
output for test purposes. Bits <7:5> of Registers 0x5C to 0x5E
(PWM Configuration) control the behavior of each PWM output.
PWM CONFIGURATION (REG. 0x5C to 0x5E)
<7:5> BHVR 111 = Manual Mode
Once under manual control, each PWM output may be manually
updated by writing to Registers 0x30 to 0x32 (PWMx current
duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWM
given by
Example 1: For a PWM duty cycle of 50%,
Value (Decimal) = 50/0.39 = 128 Decimal
Value = 128 decimal or 0x80.
Example 2: For a PWM duty cycle of 33%,
Value (Decimal) = 33/0.39 = 85 Decimal
Value = 85 Decimal or 0x54.
PWM DUTY CYCLE REGISTERS
Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% Default)
Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% Default)
Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% Default)
MIN
calibration, see the AN-613 Programming the Automatic
Value Decimal
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
(
)
=
PWM
MIN
0.39
MIN
register is
MIN
REV. C
calibra-