LM80CIMT-3/NOPB National Semiconductor, LM80CIMT-3/NOPB Datasheet - Page 17

• Manufacturer Part Number: LM80CIMT-3/NOPB
• Description: IC MONITOR SYS HARDWAR 24-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM80CIMT-3/NOPB

• Function: Hardware Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -25°C ~ 125°C, External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.8 V ~ 5.75 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Number Of Voltages Monitored: 7
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 500 ns
• Supply Voltage (max): 5.75 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 200 uA (Typ)
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 25 C
• Power Fail Detection: No
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 3°C
• Supply Current: 200µA
• Supply Voltage Range: 2.8V To 5.75V
• Resolution (bits): 8bit
• Sensor Case Style: TSSOP
• No. Of Pins: 24
• Accuracy %: 3°C
• Rohs Compliant: Yes
• For Use With: LM80EVAL - EVALUATION BOARD FOR LM80
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM80CIMT-3; *LM80CIMT-3/NOPB; LM80CIMT-3

7.2 Temperature Interrupts
There are four Value RAM WATCHDOG limits for the Tem-
perature reading that affect the INT and OS outputs of the
LM80. They are: Hot Temperature Limit, Hot Temperature
Hysteresis Limit, OS Limit, OS Hysteresis Limit. There are
three interrupt modes of operation: “One-Time Interrupt”
mode, “Default Interrupt” mode, and “Comparator Mode”. The
OS output of the LM80 can be programmed for “One-Time
Interrupt” mode and “Comparator” mode. INT can be pro-
grammed for “Default Interrupt” mode and “One-Time” Inter-
rupt.
“Default Interrupt mode” operates in the following way: Ex-
ceeding T
initely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing T
reset, an Interrupt will occur again once the next temperature
conversion has completed. The interrupts will continue to oc-
cur in this manner until the temperature goes below T
at which time the Interrupt output will automatically clear.
“One-Time Interrupt” mode operates in the following way:
Exceeding T
definitely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing T
reset, an Interrupt will not occur again until the temperature
goes below T
“Comparator” mode operates in the following way: Exceed-
ing T
remain Low until the temperature goes below T
temperature goes below T
os
causes the OS output to go Low (default). OS will
hot
hot
causes an Interrupt that will remain active indef-
hot hyst
causes an Interrupt that will remain active in-
.
os
, OS will go High.
os
. Once the
hot
hot
hot hyst
, then
, then
,
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