LTC1922EG-1#PBF Linear Technology, LTC1922EG-1#PBF Datasheet - Page 16

IC CTLR PWM SYNC 20SSOP

LTC1922EG-1#PBF

Manufacturer Part Number
LTC1922EG-1#PBF
Description
IC CTLR PWM SYNC 20SSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1922EG-1#PBF

Pwm Type
Voltage/Current Mode
Number Of Outputs
1
Frequency - Max
1MHz
Duty Cycle
99%
Buck
No
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
Yes
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Frequency-max
1MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1922EG-1#PBFLTC1922EG-1
Manufacturer:
IBM
Quantity:
942
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Part Number:
LTC1922EG-1#PBFLTC1922EG-1
Manufacturer:
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Quantity:
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OPERATIO
LTC1922-1
If RAMP and CS are connected together:
where: N = Transformer turns ratio
If RAMP and CS are separated
Current Transformer Sensing
A current sense transformer can be used in lieu of resistive
sensing with the LTC1922-1. Current sense transformers
are available in many styles from several manufacturers.
A typical sense transformer for this application will use a
1:50 turns ratio (N), so that the sense resistor value is N
times larger, and the secondary current N times smaller
than in the resistive sense case. Therefore, the sense
resistor power loss is about N times less with the trans-
former method, neglecting the transformers core and
copper losses. The disadvantages of this approach
16
R
I PEAK
P
CS
(
R
CS
0 4
.
)
I PEAK
P
V
(
0 4 .
2
L
Figure 9. R
– (
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
I
OUT
• •
O MAX
0
O
V
I PEAK
N EFF
125
(
P
( –
1
R
V
V
L
(
0
)
U
O
S
IN
O
= 2.2 H
= 0.025
= 3.3V
= 48V
f
D
)
5
CLK
A R
MIN
SENSE
10
)
OUTPUT CURRENT (A)
)
N
V
SLOPE
IN MAX
15
Power Loss vs I
(
L
MAG
20
)
)
25
• •
2
f
30
CLK
D
35
MIN
OUT
1922 • F09
40
include, higher cost and complexity, lower accuracy, core
reset/max duty cycle limitations and lower speed. Never-
theless, for very high power applications, this method is
preferred. The sense transformer primary is placed in the
same location as the ground referenced sense resistor, or
between the upper MOSFET drains in the (MA, MC) and
V
immunity to leading edge noise spikes, since gate charge
current and reflected rectifier recovery current are largely
eliminated. Figure 10 illustrates a typical current sense
transformer based sensing scheme. R
calculated the same as in the resistive case, only its value
is increased by the sense transformer turns ratio. At high
duty cycles, it may become difficult or impossible to reset
the current transformer. This is because the required
transformer reset voltage increases as the available time
for reset decreases to equalize the (volt • seconds) applied.
The interwinding capacitance and secondary inductance
of the current sense transformer form a resonant circuit
that limits the dV/dT on the secondary of the CS trans-
former. This in turn limits the maximum achievable duty
cycle for the CS transformer. Attempts to operate beyond
this limit will cause the transformer core to “walk” and
eventually saturate, opening up the current feedback loop.
Common methods to address this limitation include:
1. Reducing the maximum duty cycle by lowering the
2. Reducing the switching frequency of the converter.
3. Employ external active reset circuitry.
4. Using two CS transformers summed together.
5. Choose a CS transformer optimized for high frequency
IN
power transformer turns ratio.
applications.
. The advantage of the high side location is a greater
RAMP
CS
Figure 10. Current Transformer Sense Circuitry
FILTERING
OPTIONAL
R
SLOPE
SOURCE
R
S
MB
N:1
S
in this case is
CURRENT
TRANSFORMER
MD
SOURCE
1922 F10

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