UC3844N ON Semiconductor, UC3844N Datasheet - Page 9

• Manufacturer Part Number: UC3844N
• Description: IC CTRLR CURRENT MODE HP 8DIP
• Manufacturer: ON Semiconductor
• Type: High Performance Current Mode Controllersr

Specifications of UC3844N

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 60kHz
• Duty Cycle: 50%
• Voltage - Supply: 11.5 V ~ 25 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Frequency-max: 60kHz
• Output Voltage Range: 4.9 V to 5.1 V
• Input Voltage Range: 30 V
• Operating Temperature Range: 0 C to + 70 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: UC3844NOS

Undervoltage Lockout
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
upper and lower thresholds are 16 V/10 V for the UCX844,
and 8.4 V/7.6 V for the UCX845. The V
and lower thresholds are 3.6 V/3/4 V. The large hysteresis
and low startup current of the UCX844 makes it ideally
suited in off−line converter applications where efficient
bootstrap startup techniques later required (Figure 30). The
UCX845 is intended for lower voltage DC−to−DC converter
applications. A 36 V zener is connected as a shunt regulator
from V
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX844 is 11 V and
8.2 V for the UCX845.
Output
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ± 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever and undervoltage
lockout is active. This characteristic eliminates the need for
an external pull−down resistor.
pins for V
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the I
clamp level. The separate V
External
Sync
Input
Two undervoltage lockout comparators have been
These devices contain a single totem pole output stage that
The SOIC−14 surface mount package provides separate
Figure 18. External Clock Synchronization
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
CC
0.01
to ground. Its purpose is to protect the IC from
C
(output supply) and Power Ground. Proper
C
R
47
T
T
CC
V
ref
8(14)
4(7)
2(3)
1(1)
and the reference output (V
C
+
−
EA
R
R
supply input allows the
+
OSC
Bias
ref
2R
comparator upper
R
CC
5(9)
comparator
ref
pk(max)
http://onsemi.com
) are
9
f =
R
R
designer added flexibility in tailoring the drive voltage
independent of V
to this input when driving power MOSFETs in systems
where V
power and control ground connections in a current sensing
power MOSFET application.
Reference
tolerance at T
UC384X. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Design Considerations
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulsewidth jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to V
and V
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
C
(R
B
A
6
5
2
A
The 5.0 V bandgap reference is trimmed to ± 1.0%
Do not attempt to construct the converter on
1.44
+ 2R
Figure 19. External Duty Cycle Clamp and
B
ref
8
5.0k
1
5.0k
)C
+
−
+
−
CC
may be required depending upon circuit layout.
MC1455
R
S
is greater the 20 V. Figure 23 shows proper
D
Multi−Unit Synchronization
Q
J
max
4
= 25°C on the UC284X, and ± 2.0% on the
=
CC.
R
A
R
+ 2R
A zener clamp is typically connected
B
7
3
B
8(14)
4(7)
2(3)
1(1)
To
Additional
UCX84XA’s
+
−
EA
R
R
+
OSC
Bias
2R
R
CC
, V
5(9)
C
,