LP8720TLE/NOPB National Semiconductor, LP8720TLE/NOPB Datasheet - Page 20
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LP8720TLE/NOPB
Manufacturer Part Number
LP8720TLE/NOPB
Description
IC REG BUCK 5-LDO I2C 20USMD
Manufacturer
National Semiconductor
Datasheet
1.LP8720TLENOPB.pdf
(24 pages)
Specifications of LP8720TLE/NOPB
Topology
Step-Down (Buck) Synchronous (1), Linear (LDO) (5)
Function
Any Function
Number Of Outputs
6
Frequency - Switching
2MHz
Voltage/current - Output 1
0.8 V ~ 2.3 V, 400mA
Voltage/current - Output 2
1.2 V ~ 3.3 V, 300mA
Voltage/current - Output 3
1.2 V ~ 3.3 V, 300mA
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
2.7 V ~ 4.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-MicroSMD
Voltage - Output
0.8 ~ 2.3 V
Voltage - Input
3 ~ 4.5 V
Applications
Converter, Power Requirement Solution
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LP8720TLETR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LP8720TLE/NOPB
Manufacturer:
TI
Quantity:
118 432
Part Number:
LP8720TLE/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
www.national.com
”ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each
byte transfer. The receiver sends an acknowledge signal after
every byte received.
There is one exception to the “acknowledge after every byte”
rule.
When the master is the receiver, it must indicate to the trans-
mitter an end of data by not-acknowledging (“negative ac-
knowledge”) the last byte clocked out of the slave. This
“negative acknowledge” still includes the acknowledge clock
pulse (generated by the master), but the SDA line is not pulled
down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The
LP8720 operates as a slave device. Slave address is se-
lectable by IDSEL-pin.
Before any data is transmitted, the master transmits the ad-
dress of the slave being addressed. The slave device should
send an acknowledge signal on the SDA line, once it recog-
nizes its address.
The slave address is the first seven bits after a Start Condi-
tion. The direction of the data transfer (R/W) depends on the
bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system
compares this slave address with its own. If there is a match,
the device considers itself addressed and sends an acknowl-
edge signal. Depending upon the state of the R/W bit (1:read,
0:write), the device acts as a transmitter or a receiver.
When IDSEL= VBATT then slave address is 7h’7F
When IDSEL= floating (Hi-Z) then slave address is 7h’7C
When IDSEL= GND then slave address is 7h’7D
Data Read
Data Write
< > Data from master [ ] Data from slave
Address Mode
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent register
address possible
<Stop Condition>
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register
address possible
<Stop Condition>
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CONTROL REGISTER WRITE CYCLE
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CONTROL REGISTER READ CYCLE
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Master device generates start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = '0').
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the addressed
register.
Slave sends acknowledge signal.
If master will send further data bytes the control register
address will be incremented by one after acknowledge
signal.
Write cycle ends when the master creates stop condition.
Master device generates a start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = '0').
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data
direction bit (r/w = “1”).
Slave sends acknowledge signal if the slave address is
correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control
register address will be incremented by one. Slave device
sends data byte from addressed register.
Read cycle ends when the master does not generate
acknowledge signal after data byte and generates stop
condition.