LTC3831EGN#TRPBF Linear Technology, LTC3831EGN#TRPBF Datasheet - Page 10

• Manufacturer Part Number: LTC3831EGN#TRPBF
• Description: IC SW REG CONTROLLR SYNC 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC3831EGN#TRPBF

• Applications: Controller, DDR
• Voltage - Input: 3 ~ 8 V
• Number Of Outputs: 1
• Voltage - Output: 1.27 ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC3831
and source pins. In addition, connect a 0.1μF decoupling
capacitor across R
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
R
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limit-
ing circuit begins to take effect will vary from unit to unit
as the R
much as ±40% and with ±25% variation on the LTC3831’s
I
limit threshold.
The R
low. This occurs during power up, when PV
up. To prevent the high R
rent limit, the LTC3831 disables the current limit circuit
if PV
operation of the current limit circuit, PV
least 2.5V above V
when TG is low, allowing the use of an external charge
pump to power PV
Oscillator Frequency
The LTC3831 includes an onboard current controlled os-
cillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin fl oating, the oscillator runs
at about 200kHz. Every additional 1μA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V, connect-
10
MAX
LTC3831
DS(ON)
CC1
current, this can give a ±65% variation on the current
DS(ON)
CC
, the actual current limit trip point is not highly
DS(ON)
is less than 2.5V above V
+
–
is high if the V
Figure 3. Current Limit Setting
of Q1 varies. Typically, R
12μA
CC
CC1
IMAX
when TG is high. PV
.
I
R
MAX
I
12
13
FB
IMAX
to fi lter switching noise. Other-
DS(ON)
GS
1k
BG
TG
applied to the MOSFET is
from activating the cur-
0.1μF
CC
V
IN
. To ensure proper
Q1
Q2
DS(ON)
CC1
CC1
CC1
L
O
must be at
can go low
is ramping
+
+
varies as
3831 F03
C
C
IN
OUT
V
OUT
ing a 50k resistor from FREQSET to ground forces 25μA
out of the pin, causing the internal oscillator to run at
approximately 450kHz. Forcing an external 10μA current
into FREQSET cuts the internal frequency to 100kHz. An
internal clamp prevents the oscillator from running slower
than about 50kHz. Tying FREQSET to V
to run at this minimum speed.
Shutdown
The LTC3831 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN
for more than 100μs forces the LTC3831 into shutdown
mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831 supply current drops to <10μA, although off-
state leakage in the external MOSFETs may cause the total
V
temperatures. If SHDN returns high, the LTC3831 reruns
a soft-start cycle and resumes normal operation.
External Clock Synchronization
The LTC3831 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3831 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low. This forces the LTC3831 internal oscillator to
lock to the external clock frequency.
The LTC3831 internal oscillator can be externally syn-
chronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
this clock signal must not be >100μs or else the LTC3831
enters into the shutdown mode.
Figure 4 describes the operation of the external synchroni-
zation function. A negative transition at the SHDN pin forces
the internal ramp signal low to restart a new PWM cycle.
Notice that the ramp amplitude is lowered as the external
clock frequency goes higher. The effect of this decrease
in ramp amplitude increases the open-loop gain of the
IN
current to be somewhat higher, especially at elevated
CC
forces the chip
3831fb