DPA424SN Power Integrations, DPA424SN Datasheet - Page 10
![IC CONV DC-DC DPA SWITCH SPAK](/photos/7/56/75626/596-mo-169-7c_sml.jpg)
DPA424SN
Manufacturer Part Number
DPA424SN
Description
IC CONV DC-DC DPA SWITCH SPAK
Manufacturer
Power Integrations
Series
DPA-Switch®r
Specifications of DPA424SN
Applications
Converter, Power Over Ethernet and Telecom Applications
Voltage - Input
16 ~ 75 V
Number Of Outputs
1
Voltage - Output
220V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SPak (5 leads + Tab)
Mounting Style
SMD/SMT
For Use With
596-1195 - KIT REF DES DPA 6.6W DC-DC CONV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Quantity:
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the transformer increases in the positive direction during t
and resets to zero during the interval t
in the magnetizing inductance is removed during t
the reset capacitor and the clamp capacitor to maximum voltage.
The flux increases in the negative direction during the interval
t
into the magnetizing inductance. The flux remains a constant
negative value during the interval t
transformer windings is zero. It is easy to see that the primary
voltage is zero during t
as the input of 72 V. The negative magnetizing current circulates
in the secondary winding during t
Figure 7(b) shows the drain voltage on the same circuit when
it operates at the nominal input of 48 VDC. The larger duty
ratio is consistent with the lower input voltage. Note that the
intervals t
is nearly zero.
Figure 7(c) shows the situation at input voltage of 36 VDC, with
a corresponding larger duty ratio. The transformer has reset to
zero flux because the drain voltage has reached its peak during
the interval t
flux when the DPA-Switch turns on.
Peak drain voltage under normal operating conditions should be
less than 150 V. This includes peaks in the drain voltage from the
reset of both leakage inductance and magnetizing inductance.
Figure 8 shows three cases of improper transformer reset. The
prototype example has been modified to create these illustrations.
The RC network has been removed from the output rectifier to
obtain the waveform in Figure 8(a). The clamp capacitor C
the primary is 47 pF. The magnetizing energy resets into only
the clamp capacitor and other stray capacitance. Consequently,
at 72 V input the drain voltage goes higher than desired. The
figure shows the maximum drain voltage at 152 V, in contrast
to 140 V in Figure 7(a) with a proper reset network. The Zener
clamp voltage of 150 V is specified at a current of 1 mA.
Although the Zener clamp just barely conducts at 152 V, there
is not sufficient margin in this design to tolerate a transformer
with lower primary inductance.
Figure 8(b) illustrates the situation of too much capacitance. The
RC reset network has been restored with a proper capacitance
of 2.2 nF, but C
value. The waveform shows operation at 36 VDC input and
full load. The flux in the transformer has just barely reset to
zero, as the DPA-Switch turns on at the end of the t
A larger magnetizing inductance or a lower input voltage would
not allow the transformer to reset.
The final example of an improper transformer reset is
Figure 8(c). Primary clamp capacitor C
RN
10
as the reset capacitor and the clamp capacitor discharge
C
7/04
AN-31
RZ
and t
RZ
. The drain voltage is in the region of negative
CP
RN
is increased to 470 pF, ten times the original
are the same as at 72 V input, but now t
V0
because the drain voltage is the same
V0
V0
.
, where the voltage on the
RZ
. All the energy stored
CP
is restored to its
RZ
RZ
to charge
interval.
CP
ON
on
V0
,
original value of 47 pF, but the reset capacitor is increased to
47 nF. The converter is operating at 36 VDC. The drain voltage
shows clearly that the transformer is not resetting completely.
The DPA-Switch turns on within the interval t
the transformer has not returned to zero. A small change in
operating conditions could cause the transformer to saturate
on every cycle or to run so close to saturation that it could not
accommodate change in duty ratio from a load step.
Output Capacitors
The ripple current in the output inductor generates a voltage ripple
on the output capacitors. Part of the ripple voltage comes from
the integration of the current by the capacitance, and part comes
from the voltage that appears across the capacitorʼs equivalent
series resistance (ESR). The capacitor must be selected such that
the capacitance is high enough and the ESR is low enough to
give acceptable voltage ripple with the chosen output inductor.
Usually most of the ripple voltage comes from the ESR. Ripple
voltage that is dominated by ESR has a triangular waveform
like the ripple current in the inductor. Ripple voltage that is
dominated by the capacitance has a waveform with segments
that are parabolic instead of linear.
Output capacitors in DC-DC converters are typically solid
tantalum. They are a good choice because of their low ESR and
low impedance at the frequencies used in these converters. The
ESR is also an important element in the design of the feedback
loop. In this regard, a moderate amount of ESR is desirable.
The section on Feedback Design elaborates on the values of
the components in the feedback circuit.
It is important for designers to know that the value of ESR
may change significantly over the specified temperature range.
The output ripple and the stability of the control loop can be
affected by the change in ESR. It is necessary to evaluate
prototype hardware at the extremes of temperature to confirm
satisfactory performance.
The voltage rating for the capacitors is typically 25% higher
than the maximum operating voltage for reliability. The derating
factor is thus 80%. For example, a 5 V output would have a
capacitor that is rated for either 6.3 V or 10 V. The lower voltage
capacitor would be smaller, whereas the higher voltage capacitor
would have a lower failure rate in the application.
Feedback Design
Stability is an important consideration for a switching power
supply. Three parameters that describe the characteristics of the
control loop are crossover frequency, phase margin and gain
margin. The crossover frequency is the frequency where the
magnitude of the loop gain passes through 0 dB. It is a measure
of the systemʼs bandwidth.
RZ
. The flux in