SC418ULTRT Semtech, SC418ULTRT Datasheet - Page 18

• Manufacturer Part Number: SC418ULTRT
• Description: IC BUCK SYNC ADJ 20MLPQ
• Manufacturer: Semtech
• Series: EcoSpeed™, SmartDrive™r
• Type: Step-Down (Buck)r

Specifications of SC418ULTRT

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 5.5 V
• Frequency - Switching: 200kHz ~ 1MHz
• Voltage - Input: 3 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-MLPQ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Other names: SC418ULTRTTR

Applications Information (continued)
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation the average current through the inductor is 10A
plus one-half the peak-to-peak ripple current.
The R
The internal 10μA current source is temperature compen-
sated at 4100ppm in order to provide tracking with the
RDS
Note that MOSFET RDS
VDDP voltage is 3.3V compared to 5.0V. When selecting
the R
the VDDP voltage used in the application.
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB compara-
tor. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
500mV in 1.2mV increments, using an internal 500kHz
oscillator. When the ramp voltage reaches 500mV, the
ramp is ignored and the FB comparator switches over to a
fixed 500mV threshold. During soft-start the output
voltage tracks the internal ramp, which limits the start-up
inrush current and provides a controlled soft-start profile.
Typical soft-start ramp time is 850μs.
PGND
ON
R
ILIM
BST
DH
LX
ILIM
DL
ILIM
ILIM
.
value is calculated by the next equation.
value, use the RDS
R
Figure 9 — Valley Current Limit
DSON
10
A
I
LIM
C
V
R
IN
BST
ILIM
(ON)
Q1
Q2
(ON)
increases significantly if the
value that corresponds to
D2
+
CIN
L
C
OUT
+
V
OUT
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero,
regardless of the psave setting. This prevents negative
inductor current, allowing the device to start into a pre-
biased output.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 10% below the nominal voltage, PGOOD is pulled
low. It remains low until the FB voltage returns above -8%
of nominal. During start-up PGOOD is held low and will
not be allowed to transition high until the PGOOD start-
up delay fime has passed and soft-start is completed
(when V
EN going high is typically 2ms for VDDA = 5V and 1ms for
VDDA = 3.3V.
PGOOD will transition low if the FB voltage exceeds +20%
of nominal (600mV), which is also the over-voltage shut-
down threshold. PGOOD also pulls low if the EN pin is low
when VDDA is present.
Output Over-Voltage Protection
OVP (Over-voltage protection) becomes active as soon as
the device is enabled. The OVP threshold is set at 500mV
+ 20% (600mV). When V
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off until the EN
input is toggled or VDDA is cycled. There is a 5μs delay
built into the OVP detector to prevent false transitions.
PGOOD is also low after an OVP event.
Output Under-Voltage Protection
When V
375mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-
state the MOSFETs. The controller stays off until EN is
toggled or VDDA is cycled.
VDDA UVLO and POR
The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib-
its switching and tri-states the DH/DL drivers until VDDA
rises above 2.9V. When VDDA exceeds 2.9V, an internal
POR (Power-On Reset) resets the fault latch and the soft-
start counter and then the SC418 begins the soft-start
FB
FB
reaches 500mV). The delay time starting from
falls 25% below its nominal voltage (falls to
FB
exceeds the OVP threshold, DL
SC418
18