SC2463TSTRT Semtech, SC2463TSTRT Datasheet - Page 19

• Manufacturer Part Number: SC2463TSTRT
• Description: IC QUAD OUTPUT SW REG HP 28TSSOP
• Manufacturer: Semtech
• Type: Step-Down (Buck)r

Specifications of SC2463TSTRT

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: Adj to 0.5V
• Frequency - Switching: 100kHz ~ 700kHz
• Voltage - Input: 4.5 ~ 30 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Power - Output: 1.3W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Other names: SC2463TSTR

3. Select
4. Cancel
5. Place a high frequency compensation pole
The compensated loop gain will be as given in Figure 8:
Figure 8. Asymptotic diagram of buck power stage and
its compensated loop gain
Dual Positive LDOs Controller
The SC2463 provides two positive adjustable linear regu-
lator controllers. The first positive linear regulator uses a
PNP transistor to regulate output voltage. This is set by
a voltage divider connected from the output to FB to
AGND. Referring to the front page Application Circuit,
select R10 in the 5K to 20K range. Calculate R9 with
the following equation:
The second positive linear regulator uses a NPN transis-
tor to regulate output voltage. This is set by a voltage
divider connected from the output to FB to AGND. Re-
ferring to the front page Application Circuit, select R18
in the 5K
following equation:
POWER MANAGEMENT
Applications Information (Cont.)
2007 Semtech Corp.
to dampen peaking; the loop gain has –20dB rate
to go across the 0dB line for obtaining a wide band-
width.
half switching frequency to get the maximum attenu-
ation of the switching ripple and the high frequency
noise with the adequate phase lag at
T (s)
T (s)
G vd
G vd
0d B
0d B
to 20K
Z1
ESR
P o w e r st a ge
P o w e r st a ge
and
G
G
with compensation pole
V D
V D
(s)
(s)
-4 0d B / de c
-4 0d B / de c
R
R
z1
z1
Z2
14
9
range. Calculate R14 with the
such that they are placed near
o
o
R
R
10
18
z2
z2
V
V
0
0
OUT
c
c
OUT
5 .
5 .
Lo op ga i n T (s)
Lo op ga i n T (s)
E S R
E S R
1
1
p 1
p 1
-2 0d B / de c
-2 0d B / de c
p 2
p 2
P1
(
C
.
P1
P2
=
at the
ESR
).
O
19
Layout Guidelines
Layout Guidelines
The maximum voltage to drive an NPN transistor is AVCC
minus the voltage drop across the internal P-MOSFET
which is the product of On-Resistance and sourcing cur-
rent. The maximum driving voltage with 5mA sourcing
current is minimum AVCC (4.5V) minus 5mA times maxi-
mum On-Resistance 140 , i.e. 3.8V.
Layout Guidelines
Layout Guidelines
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, attention
must be paid to the PCB layouts. The goal of layout opti-
mization is to place components properly and identify
the high di/dt loops to minimize them. The following guide-
lines should be used to ensure proper functions of the
converters:
1. A ground plane is recommended to minimize noises
2. Start the PCB layout by placing the power compo-
3. The PVCC and AVCC bypass capacitors should be
4. Separate the power ground from the signal ground.
5. The trace connecting the feedback resistors to the
7. Minimize the loop including input capacitors, top/bot-
8. Maximize the trace width of the loop connecting the
9. Connect the ground of the feedback divider and the
and copper losses, and maximize heat dissipation.
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
placed next to the PVCC, AVCC and PGND, AGND pins
respectively.
In SC2463, the power ground PGND should be tied
to the source terminal of lower MOSFETs. The signal
ground AGND should be tied to the negative termi-
nal of the output capacitor.
output should be short, direct and far away from the
noise sources such as switching node and switching
components. Minimize the traces between DRXH/
DRXL and the gates of the MOSFETs to reduce their
impedance to drive the MOSFETs.
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
inductor, bottom MOSFET and the output capacitors.
compensation components directly to the GND pin
of the SC2463 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
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