MAX15041ETE+ Maxim Integrated Products, MAX15041ETE+ Datasheet - Page 13
![IC DCDC CONV STP-DN SYNC 16TQFN](/photos/29/10/291044/qfn16_sml.jpg)
MAX15041ETE+
Manufacturer Part Number
MAX15041ETE+
Description
IC DCDC CONV STP-DN SYNC 16TQFN
Manufacturer
Maxim Integrated Products
Type
Step-Down (Buck)r
Datasheet
1.MAX15041ETE.pdf
(18 pages)
Specifications of MAX15041ETE+
Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.6 ~ 25.2 V
Current - Output
3A
Frequency - Switching
350kHz
Voltage - Input
4.5 ~ 28 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Power - Output
1.67W
Output Voltage
5.1 V
Supply Current
2.1 mA
Switching Frequency
350 KHz
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 1. Peak Current-Mode Regulator Transfer Model
Having defined the power modulator’s transfer function
gain, the total system loop gain can be written as fol-
lows (see Figure 1):
where R
gain, A
ductance, g
much larger than C
Rewriting:
Step-Down DC-DC Regulator with Internal Switches
Gain
FEEDBACK
R
R
DIVIDER
1
2
V
OUT
s C
VEA
V
G
C
OUT
V
OUT
MOD LOAD
FB
REF
G
, divided by the error amplifier’s transcon-
C
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
FB
MV
MOD
CC
is the quotient of the error amplifier’s DC
A
R
; R
Gain
VEA
g
MV
R
C
OUT
______________________________________________________________________________________
R
CC
LOAD
ERROR AMPLIFIER
*C
R
R
R
OUT
CC
.
1
sC
is much larger than R
R
OUT
R
OUT
s s C
IS OPTIONAL.
2
C
= A
R
OUT
R
sC
2
1
OUT
VEA
A
sC R
g
sC
OUT
VEA
MV
/g
R
A
C C
ESR R
MV
sC
s C
OUT
OUT
VEA
sC R
ESR R
O
C C
U U T
R
C C
ESR
C
C
1
||
C
1 1
ESR
COMP
C
LOAD
CC
LOAD
*C
1
1
sC
1
R
CC
C
CC C
C
||
1
R
and C
1
R
NOTE: THE G
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
OUT
COMPARATOR
1
C
PWM
1
is
MOD
STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
COMPENSATION
The dominate poles and zeros of the transfer loop gain
is shown below:
The order of pole-zero occurrence is:
Note under heavy load, f
A graphical representation of the asymptotic system
closed-loop response, including the dominant pole and
zero locations is shown in Figure 2.
g
MC
CONTROL
f
f
f
P
P
Z
RAMP
LOGIC
V
1
3
2
COMP
POWER MODULATOR
2
2
2 2
G
MOD
10
C
C
1
CC C
OUT
A
1
VEA
R
g
ESR
V
MV
V
f
IN
P
dB
I
OUT
L
Q
Q
1
HS
LS
f
/
Z
20
1
f
P
L0
2
2
C
P2
C
f
Z
, may approach f
C R
1
1
f
C C
P
DCR
2
I
L
f
Z
2
2
f
P
C
3
C
OUT
ESR
OUT
OUTPUT FILTER
AND LOAD
ESR
1
Z1
.
V
OUT
R
R
LOAD
LOAD
13