LTC3865EFE#PBF Linear Technology, LTC3865EFE#PBF Datasheet - Page 27

• Manufacturer Part Number: LTC3865EFE#PBF
• Description: IC BUCK SYNC ADJ DUAL 38TSSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3865EFE#PBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 5 V
• Frequency - Switching: 250kHz ~ 770kHz
• Voltage - Input: 4.5 ~ 38 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP Exposed Pad, 38-eTSSOP, 38-HTSSOP
• Primary Input Voltage: 15V
• No. Of Outputs: 2
• Output Voltage: 5V
• Output Current: 25A
• No. Of Pins: 38
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -

APPLICATIONS INFORMATION
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R
will be increased by decreasing C
the same factor that C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited
to approximately 25 • C
require a 250μs rise time, limiting the charging current
to about 200mA.
LOAD
TH
OUT
to C
series R
, causing a rapid drop in V
OUT
is greater than 1:50, the switch rise time
C
-C
C
C
fi lter sets the dominant pole-zero
LOAD
is decreased, the zero frequency
C
and the bandwidth of the loop
. Thus a 10μF capacitor would
TH
TH
pin waveforms that will
C
. If R
pin signal which is in
OUT
. No regulator can
C
is increased by
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 12. Figure 13 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
2. Are the signal and power grounds kept separate? The
3. Do the LTC3865 V
4. Are the SENSE
5. Is the INTV
within 1 cm of each other with a common drain con-
nection at C
coupling for the two channels as it can cause a large
resonant loop.
combined IC signal ground pin and the ground return
of C
minals. The V
as possible. The path formed by the top N-channel
MOSFET, Schottky diode and the C
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
of C
and C
feeds from the input capacitor(s).
minimum PC trace spacing? The fi lter capacitor between
SENSE
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
the IC, between the INTV
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV
noise performance substantially.
INTVCC
OUT
OUT
+
? The connections between the V
and SENSE
should not be along the high current input
CC
must return to the combined C
IN
LTC3865/LTC3865-1
OSENSE
decoupling capacitor connected close to
? Do not attempt to split the input de-
+
and SENSE
OSENSE
CC
and PGND pins can help improve
–
and I
should be as close as possible
pins connect to the (+) terminals
CC
TH
and the power ground pins?
–
leads routed together with
traces should be as short
IN
capacitor should
OSENSE
OUT
27
(–) ter-
pins
3865fb