LT1676CN8 Linear Technology, LT1676CN8 Datasheet - Page 6

• Manufacturer Part Number: LT1676CN8
• Description: IC SW REG STEP-DOWN HI-EFF 8-DIP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT1676CN8

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.24 ~ 51 V
• Current - Output: 700mA
• Frequency - Switching: 100kHz
• Voltage - Input: 7.4 ~ 60 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

OPERATIO
LT1676
BLOCK DIAGRA
The LT1676 is a current mode switching regulator IC that
has been optimized for high efficiency operation in high
input voltage, low output voltage Buck topologies. The
Block Diagram shows an overall view of the system.
Several of the blocks are straightforward and similar to
those found in traditional designs, including: Internal Bias
Regulator, Oscillator and Feedback Amplifier. The novel
portion includes an elaborate Output Switch section and
Logic Section to provide the control signals required by
the switch section.
The LT1676 operates much the same as traditional
current mode switchers, the major difference being its
specialized output switch section. Due to space con-
straints, this discussion will not reiterate the basics of
current mode switcher/controllers and the “Buck” topol-
ogy. A good source of information on these topics is
Application Note 19.
6
SHDN
SYNC
GND
V
V
CC
FB
C
2
1
6
4
8
7
V
BG
U
gm
BIAS
OSC
FB
AMP
W
V
B
BOOST
COMP
V
BG
V
LOGIC
TH
SWDR
SWDR
SWON
BOOST
SWOFF
I
R1
Output Switch Theory
One of the classic problems in delivering low output
voltage from high input voltage at good efficiency is that
minimizing AC switching losses requires very fast volt-
age (dV/dt) and current (dI/dt) transition at the output
device. This is in spite of the fact that in a bipolar
implementation, slow lateral PNPs must be included in
the switching signal path.
Fast positive-going slew rate action is provided by lateral
PNP Q3 driving the Darlington arrangement of Q1 and Q2.
The extra
requirements of Q3.
Although desirable for dynamic reasons, this topology
alone will yield a large DC forward voltage drop. A second
lateral PNP, Q4, acts directly on the base of Q1 to reduce
the voltage drop after the slewing phase has taken place.
To achieve the desired high slew rate, PNPs Q3 and Q4 are
“force-fed” packets of charge via the current sources
controlled by the boost signal.
BOOST
SWON
COMP
I
I
available from Q2 greatly reduces the drive
I
SWOFF
Q4
I
Q5
Q3
Q2
D1
Q1
R
SENSE
1676 BD
5
3
V
V
IN
SW