LT3470ITS8#TRPBF Linear Technology, LT3470ITS8#TRPBF Datasheet - Page 13

• Manufacturer Part Number: LT3470ITS8#TRPBF
• Description: IC REG SW BUCK 200MA TSOT23-8
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3470ITS8#TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.25 ~ 16 V
• Current - Output: 200mA
• Voltage - Input: 4 ~ 40 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-8, TSOT-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Frequency - Switching: -

APPLICATIO S I FOR ATIO
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Note that large,
switched currents flow in the power switch, the internal
catch diode and the input capacitor. The loop formed by
these components should be as small as possible. Fur-
thermore, the system ground should be tied to the regu-
lator ground in only one place; this prevents the switched
current from injecting noise into the system ground.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board, and their connections should be made on that layer.
Place a local, unbroken ground plane below these compo-
nents, and tie this ground plane to system ground at one
SHDN
GND
V
VIAS TO FEEDBACK DIVIDER
VIAS TO LOCAL GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
IN
U
C1
U
Figure 5. A Good PCB Layout Ensures Proper, Low EMI Operation
(A)
C2
W
U
V
OUT
V
location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BOOST nodes
should be kept as small as possible. Unshielded inductors
can induce noise in the feedback path resulting in instabil-
ity and increased output ripple. To avoid this problem, use
vias to route the V
feedback divider (as shown in Figure 5). Finally, keep the
FB node as small as possible so that the ground pin and
ground traces will shield it from the SW and BOOST nodes.
Figure 5 shows component placement with trace, ground
plane and via locations. Include vias near the GND pin, or
pad, of the LT3470 to help remove heat from the LT3470
to the ground plane.
OUT
OUT
trace under the ground plane to the
(B)
3470 F05
LT3470
SHDN
V
GND
IN
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