LT3500EDD#TRPBF Linear Technology, LT3500EDD#TRPBF Datasheet - Page 22

• Manufacturer Part Number: LT3500EDD#TRPBF
• Description: IC REG STP-DWN 2A 12-DFN
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3500EDD#TRPBF

• Topology: Step-Down (Buck) (1), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 2
• Frequency - Switching: 500kHz ~ 2.4MHz
• Voltage/current - Output 1: 0.8 ~ 38.9 V, 2A
• Voltage/current - Output 2: Adjustable, 13mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 3 V ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 12-DFN
• Current - Output: 2A
• Voltage - Output: 0.8 ~ 38.9 V
• Voltage - Input: 3 ~ 36 V
• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

LT3500
To compensate the linear regulator, simply add a ceramic
capacitor from the LDRV pin to ground. Typical values
range from 0.01μF to 1μF . Figure 9 illustrates the transient
response with a 0.47μF output capacitor.
Linear Controller
By adding an external follower (NPN or NMOS), the LFB
and LDRV pins can be confi gured as a controller (Fig-
ure 10) for a low dropout regulator with increased output
capability.
The output current capability of Figure 10’s circuit is a
product of the LDRV current limit and beta of the external
NPN which is normally less than the current capability of
the LT3500. The dropout voltage for the circuit is set by the
saturation voltage of the external NPN, which is typically
300mV. The minimum V
erly is 2V plus the base emitter drop of the external NPN.
Replacing the NPN in Figure 10 with a NMOS transistor
can reduce the dropout voltage down to the R
APPLICATIONS INFORMATION
22
2.5mA TO 7.5mA
AC COUPLED
LOAD STEP
20mV/DIV
5mA/DIV
V
Figure 9. Linear Regulator Transient Response
OUT2
IN
for the circuit to function prop-
4.5V TO 36V
20μs/DIV
R6
40.2k
0.47μF
220pF
2.2μF
C1
C2
C3
R5
49.9k
3500 F09
DS(ON)
V
SHDN
SS
R
V
IN
C
T/
Figure 10. Linear Controller
SYNC
LT3500
of the
LDRV
BST
LFB
SW
PG
PG
FB
NMOS times the output current of the regulator. This also
increases the overall effi ciency of the system. However,
the minimum V
of the transistor. Additionally, due to a lack of beta current
limiting, a shorted output can cause the switcher output
of the LT3500 to collapse.
Since the collector of the LDRV npn is connected internally
to V
effi ciency and die temperature when confi guring the linear
regulator/controller. For example, with V
3.3V and I
be 217mW. For a typical 3.3V/1A switcher application,
this represents an additional 7% effi ciency loss and ap-
proximately 10 degrees rise in die temperature.
If the linear output of the LT3500 is not used, the LDRV
pin should be shorted to the LFB Pin.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 11
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents fl ow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
one location, ideally at the ground terminal of the output
C5
0.47μF
D1
B240A
IN
3.3μH
, you must consider the impact of LDRV current on
L1
27.4k
R1
LDRV
BAT54
D2
8.06k
R4
8.06k
24.9k
R2
R3
IN
= 10mA, power dissipation on the die will
increases to 2V plus the V
C7
22μF
3500 F10
V
3.5V
C6
22μF
V
3.3V
1A
OUT1
OUT2
IN
= 25V, LDRV =
GS
at full load
3500fc