LTC1266CS Linear Technology, LTC1266CS Datasheet - Page 14

• Manufacturer Part Number: LTC1266CS
• Description: IC REG CNTRLR N/PCH MOSFET16SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LTC1266CS

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Current - Output: 50mA
• Frequency - Switching: 400kHz
• Voltage - Input: 3.5 ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
LTC1266
LTC1266-3.3/LTC1266-5
discharge C
current change and returns V
During this recovery time V
overshoot or ringing which would indicate a stability
problem. The Pin 7 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits, only small
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1266 series circuits: 1) LTC1266 DC bias
current, 2) MOSFET gate charge current and 3) I
1. The DC supply current is the current which flows into
V
is 170 A for no load, and increases proportionally with
load up to a constant 2.1mA after the LTC1266 series has
entered continuous mode. Because the DC bias current is
drawn from V
voltage. For V
than 1% for load currents over 30mA. However, at very
low load currents the DC bias current accounts for nearly
all of the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again, a
packet of charge dQ moves from Power V
resulting dQ/dt is a current flowing into Power V
which is typically much larger than the DC supply current.
In continuous mode, I
gate charge for a 0.05
14
IN
% Efficiency = 100% – (L1 + L2 + L3 + ...)
(Pin 2). For V
OUT
IN
IN
= 5V the DC bias losses are generally less
, the resulting loss increases with input
IN
until the regulator loop adapts to the
= 10V the LTC1266 DC supply current
U
GATECHG
U
N-channel power MOSFET is
OUT
OUT
= f (Q
to its steady-state value.
can be monitored for
W
N
+ Q
IN
to ground. The
P
). The typical
U
2
IN
R losses.
(Pin 5)
15nC. This results in I
ous operation for a 2% to 3% typical mid-current loss with
V
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits oper-
ate at moderate frequencies. Furthermore, it argues against
using larger MOSFETs than necessary to control I
losses, since overkill can cost efficiency as well as money!
3. I
of the MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
R
tom-side MOSFETs. If the two MOSFETs have approxi-
mately the same R
MOSFET can simply be summed with the resistances of L
and R
R
the total resistance is 0.12 . This results in losses ranging
from 3.5% to 15% as the output current increases from 1A
to 5A. I
output currents.
Figure 8 shows how the efficiency losses in a typical
LTC1266 series regulator end up being apportioned. The
gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
unacceptable levels (see Figure 7). With Burst Mode
IN
SENSE
DS(ON)
Note that the gate charge loss increases directly with
2
= 5V.
R losses are easily predicted from the DC resistances
SENSE
, but is “chopped” between the topside and bot-
2
= 0.05 , R
R losses cause the efficiency to roll off at high
100
95
90
85
80
0.01
to obtain I
LTC1266 I
GATE CHARGE
0.03
Figure 8. Efficiency Loss
L
Q
DS(ON)
= 0.05 and R
GATECHG
2
0.1
R losses. For example, if each
I
OUT
, then the resistance of one
(A)
0.3
= 6mA in 200kHz continu-
SENSE
1
I
1266 F08
2
R
5
= 0.02 , then
2
R