LTC3736EUF-2#TRPBF Linear Technology, LTC3736EUF-2#TRPBF Datasheet - Page 22

• Manufacturer Part Number: LTC3736EUF-2#TRPBF
• Description: IC CTRLR SW SYNC DUAL 2PH 24QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3736EUF-2#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 9.8 V
• Current - Output: 1A
• Frequency - Switching: 550kHz ~ 750kHz
• Voltage - Input: 2.75 ~ 9.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

continuous applications with low ripple current at light
loads. If forced continuous mode is selected and the duty
cycle falls below the minimum on-time requirement, the
output will be regulated by overvoltage protection.
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting effi ciency and which change would produce the
most improvement. Effi ciency can be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, fi ve main sources usually account for most of the
losses in LTC3736-2 circuits: 1) LTC3736-2 DC bias cur-
rent, 2) MOSFET gate charge current, 3) I
4) transition losses.
1. The V
2. MOSFET gate charge current results from switching the
3. I
APPLICATIONS INFORMATION
LTC3736-2
22
Effi ciency = 100% – (L1 + L2 + L3 + …)
in the electrical characteristics, excluding MOSFET
driver currents. V
increases with V
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE
The resulting dQ/dt is a current out of SENSE
is typically much larger than the DC supply current. In
continuous mode, I
the MOSFETs and inductor. In continuous mode, the
average output current fl ows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET R
by duty cycle can be summed with the resistance of L
to obtain I
2
R losses are calculated from the DC resistances of
IN
(pin) current is the DC supply current, given
2
R losses.
IN
IN
.
GATECHG
current results in a small loss that
= f • Q
P
.
DS(ON)
2
R losses, and
+
s multiplied
to ground.
+
, which
4. Transition losses apply to the top external P-channel
Other losses, including C
and inductor core losses, generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (ΔI
resistance of C
charge C
The regulator loop then returns V
value. During this recovery time, V
for overshoot or ringing. OPTI-LOOP
lows the transient response to be optimized over a wide
range of output capacitance and ESR values.
The I
dominant pole-zero loop compensation. The I
components shown in the Typical Application on the front
page of this data sheet will provide an adequate starting
point for most applications. The values can be modifi ed
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the fi nal PC layout is done
and the particular output capacitor type and value have
been determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and I
pin waveforms that will give a sense of the overall loop
stability. The gain of the loop will be increased by increas-
ing R
by decreasing C
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
MOSFET and increase with higher operating frequencies
and input voltages. Transition losses can be estimated
from:
Transition Loss = 2 (V
TH
C
, and the bandwidth of the loop will be increased
series R
OUT
LOAD
, which generates a feedback error signal.
C
OUT
C
-C
)(ESR), where ESR is the effective series
. The output voltage settling behavior is
C
. ΔI
fi lter (see Functional Diagram) sets the
OUT
LOAD
IN
immediately shifts by an amount
IN
and C
)
also begins to charge or dis-
2
I
O(MAX)
OUT
OUT
OUT
ESR dissipative losses
C
®
RSS
to its steady-state
can be monitored
compensation al-
(f)
TH
external
37362fb
TH