LT1374CFE#TRPBF Linear Technology, LT1374CFE#TRPBF Datasheet - Page 21
![IC SW REG 4.5A ADJ STPDN 16TSSOP](/photos/7/34/73402/161-16-tssop_sml.jpg)
LT1374CFE#TRPBF
Manufacturer Part Number
LT1374CFE#TRPBF
Description
IC SW REG 4.5A ADJ STPDN 16TSSOP
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet
1.LT1374CFEPBF.pdf
(32 pages)
Specifications of LT1374CFE#TRPBF
Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
2.42 ~ 21.5 V
Current - Output
4.5A
Frequency - Switching
500kHz
Voltage - Input
5 ~ 25 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
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APPLICATIONS
THERMAL CALCULATIONS
Power dissipation in the LT1374 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
Boost current loss:
Quiescent current loss:
R
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
SW
= Switch resistance (≈ 0.07)
IN
= 10V, V
U
INFORMATION
U
OUT
= 5V and I
W
OUT
= 3A:
U
Thermal resistance for LT1374 package is influenced by
the presence of internal or backside planes. With a full
plane under the 16-lead TSSOP package, thermal resis-
tance will be about 40°C/W. To calculate die temperature,
use the proper thermal resistance number for the desired
package and add in worst-case ambient temperature:
With the TSSOP16 package (θ
temperature of 50°C,
For the DD package with a good copper plane under the
device, thermal resistance will be about 30°C/W. For the
conditions above:
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180° phase shift at the resonant
frequency. By contrast, the LT1374 uses a “current mode”
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1374, measured from the V
the output. Gain is set by the 5.3A/V transconductance of
the LT1374 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 600Hz pole frequency set by the 100µF output
capacitor. Phase drop is limited to about 70°. Phase
recovers and gain levels off at the zero frequency (≈16kHz)
set by capacitor ESR (0.1Ω).
T
T
T
J
J
J
= T
= 50 + 40 (0.87) = 85°C
= 50 + 30 (0.87) = 76°C
A
+ θ
JA
(P
TOT
)
JA
= 40°C/W), at an ambient
LT1374
21
C
pin to
1374fd