LTC1702ACGN Linear Technology, LTC1702ACGN Datasheet - Page 22
![IC REG SW DUAL SYNC 2PH 24SSOP](/photos/6/59/65961/161-24-ssop_sml.jpg)
LTC1702ACGN
Manufacturer Part Number
LTC1702ACGN
Description
IC REG SW DUAL SYNC 2PH 24SSOP
Manufacturer
Linear Technology
Series
PolyPhase®r
Type
Step-Down (Buck)r
Datasheet
1.LTC1702ACGNPBF.pdf
(36 pages)
Specifications of LTC1702ACGN
Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
2
Voltage - Output
0.8 ~ 7 V
Current - Output
1A, 25A
Frequency - Switching
550kHz
Voltage - Input
3 ~ 7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1702ACGN
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC1702ACGN#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC1702ACGN#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS
LTC1702A
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC1702A circuits using
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with type 2
compensation.
“Type 3” loops (Figure 11) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a type 2 circuit, the
loop should cross through 0dB in the middle of the phase
bump to maximize phase margin. Many LTC1702A cir-
cuits using low ESR tantalum or OS-CON output capaci-
22
Figure 11a. Type 3 Amplifier Schematic Diagram
GAIN
Figure 11B. Type 3 Amplifier Transfer Function
(dB)
0
IN
GAIN
PHASE
–6dB/OCT
C3
U
R1
R
B
R3
+6dB/OCT
INFORMATION
U
V
REF
R2
+
–
C2
C1
W
–6dB/OCT
1702A F11a
OUT
1702A F11b
PHASE
0
–90
–180
–270
(DEG)
U
tors need type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
Feedback Component Selection
Selecting the R and C values for a typical type 2 or type 3
loop is a nontrivial task. The applications shown in this data
sheet show typical values, optimized for the power com-
ponents shown. They should give acceptable performance
with similar power components, but can be way off if even
one major power component is changed significantly.
Applications that require optimized transient response will
need to recalculate the compensation values specifically
for the circuit in question. The underlying mathematics are
complex, but the component values can be calculated in a
straightforward manner if we know the gain and phase of
the modulator at the crossover frequency.
Modulator gain and phase can be measured directly from
a breadboard, or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurate results, but simulation can often get close enough
to give a working system. To measure the modulator gain
and phase directly, wire up a breadboard with an LTC1702A
and the actual MOSFETs, inductor, and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC1702A, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple type 1 loop, with a 10k resistor from
V
FB. Choose the bias resistor (R
desired output voltage. Disconnect R
connect it to a signal generator or to the source output of
a network analyzer (Figure 12) to inject a test signal into
the loop. Measure the gain and phase from the COMP pin
to the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and V
nodes don’t corrupt the measurements or damage the
analyzer.
OUT
to FB and a 0.1µF feedback capacitor from COMP to
B
) as required to set the
B
from ground and
1702afa
OUT