LTC3728EG#TRPBF Linear Technology, LTC3728EG#TRPBF Datasheet - Page 16

IC SW REG SYNC STP-DN DUAL28SSOP

LTC3728EG#TRPBF

Manufacturer Part Number
LTC3728EG#TRPBF
Description
IC SW REG SYNC STP-DN DUAL28SSOP
Manufacturer
Linear Technology
Series
PolyPhase®r
Type
Step-Down (Buck)r
Datasheet

Specifications of LTC3728EG#TRPBF

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
2
Voltage - Output
0.8 ~ 5.5 V
Current - Output
3A
Frequency - Switching
250kHz ~ 550kHz
Voltage - Input
3.5 ~ 36 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-

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APPLICATIONS INFORMATION
LTC3728
load transient response and suffi cient ripple current sig-
nal in the current loop. The maximum ΔI
maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R
inductor values (higher ΔI
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mμ
size for a fi xed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ. Toroids are very space effi cient,
especially when you can use several layers of wire. Because
they generally lack a bobbin, mounting is more diffi cult.
However, designs for surface mount are available that do
not increase the height signifi cantly.
16
®
cores. Actual core loss is independent of core
L
) will cause this to occur at
L
SENSE
occurs at the
. Lower
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the LTC3728: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
voltage. This voltage is typically 5V during start-up
(see EXTV
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V
< 3V) should be used. Pay close attention to the BV
specifi cation for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R
input voltage and maximum output current. When the
LTC3728 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
The MOSFET power dissipations at maximum output
current are given by:
where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.
Both MOSFETs have I
equation includes an additional term for transition losses,
IN
Main Switch Duty Cycle =
P
P
Synchronous Switch Duty Cycle =
MAIN
SYNC
< 5V); then, sublogic level threshold MOSFETs (V
=
=
k V
CC
( )
V
V
V
OUT
IN
Pin Connection). Consequently, logic-level
IN
IN
DS(ON)
– V
V
2
IN
(
I
(
MAX
OUT
I
MAX
2
R losses while the topside N-channel
, reverse-transfer capacitance C
)
(
2
I
)
MAX
(
(
C
1+
RSS
)
V
2
V
OUT
)
(
)
IN
R
1+
( )
f
DS(ON)
)
R
V
IN
DS(ON)
+
– V
V
IN
DS(ON)
OUT
GS(TH)
and k
RSS
3728fg
DSS
CC
,

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