LTC3728EUH#TR Linear Technology, LTC3728EUH#TR Datasheet - Page 26

• Manufacturer Part Number: LTC3728EUH#TR
• Description: IC SW REG SYNC STP-DN DUAL 32QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728EUH#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3728EUHTR

APPLICATIONS INFORMATION
LTC3728
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by ensuring C
charge storage and very low ESR at the switching frequency.
A 25W supply will typically require a minimum of 20μF
to 40μF of capacitance having a maximum of 20mΩ to
50mΩ of ESR. The LTC3728 2-phase architecture typically
halves this input capacitance requirement over competing
solutions. Other losses, including Schottky conduction
losses during dead time and inductor core losses, generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
an amount equal to ΔI
fective series resistance of C
charge or discharge C
signal that forces the regulator to adapt to the current
change and return V
26
4. Transition losses apply only to the topside MOSFET(s),
R
and output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Effi ciency varies as the inverse square of V
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V
SENSE
= 10mΩ and R
OUT
OUT
LOAD
to its steady-state value. During
ESR
, generating the feedback error
IN
(ESR), where ESR is the ef-
= 40mΩ (sum of both input
2
OUT
I
O(MAX)
. ΔI
LOAD
C
RSS
IN
also begins to
has adequate
OUT
f
OUT
shifts by
for the
this recovery time, V
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
not only allows optimization of control loop behavior but
also provides a DC-coupled and AC-fi ltered closed loop
response test point. The DC step, rise time and settling
at this test point truly refl ects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The I
circuit will provide an adequate starting point for most
applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
in the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R
will be increased by decreasing C
the same factor that C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
TH
series R
TH
external components shown in the Figure 1
C
-C
C
OUT
fi lter sets the dominant pole-zero
C
is decreased, the zero frequency
C
can be monitored for excessive
and the bandwidth of the loop
TH
pin waveforms that will
C
TH
. If R
pin signal, which is
C
is increased by
TH
3728fg
pin