IR3876MTRPBF International Rectifier, IR3876MTRPBF Datasheet
IR3876MTRPBF
Specifications of IR3876MTRPBF
Related parts for IR3876MTRPBF
IR3876MTRPBF Summary of contents
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SupIRBuck TM WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR Features Input Voltage Range 21V Output Voltage Range: 0.5V to 12V Continuous 12A Load Capability Constant On-Time control Excellent Efficiency at very low output current levels ...
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... These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PACKAGE INFORMATION 5mm x 6mm POWER QFN ORDERING INFORMATION PKG DESIG M M PACKAGE PIN COUNT DESCRIPTION IR3876MTRPbF 17 IR3876TR1PbF 17 IR3876MBF θ ...
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Block Diagram IR3876MBF 3 ...
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Pin Description NAME NUMBER I/O LEVEL NC 1 ----- ISET 2 PGOOD 3 5V GND 4,17 Reference ----- 3VCBP 8 3. ----- VCC 10 5V PGND 11 Reference PHASE 12 ...
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Recommended Operating Conditions Symbol Definition VIN Input Voltage VCC Supply Voltage V Output Voltage OUT I Output Current OUT Fs Switching Frequency T Junction Temperature J * Note: PHASE pin must not exceed 25V. Electrical Specifications Unless otherwise specified, these ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0 PARAMETER GATE DRIVE Dead Time BOOTSTRAP PFET Forward Voltage UPPER MOSFET Static Drain-to-Source On- Resistance LOWER MOSFET Static Drain-to-Source On- Resistance LOGIC INPUT ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V 300kHz unless otherwise specified 95% 85% 75% 16V IN 65% 12. 45% ...
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TYPICAL APPLICATION CIRCUIT Demoboard Schematic: VOUT = 1.05V 300kHz Figure 7. Typical Application Circuit for VOUT = 1.05V 300kHz Bill of Materials IR3876MBF 8 ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V 300kHz unless otherwise specified EN PGOOD SS VOUT 5V/div 5V/div 1V/div 500mV/div Figure 8: Startup VOUT ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V 300kHz unless otherwise specified VOUT PHASE i L 50mV/div 10V/div 5A/div Figure 14: Load Transient 0-8A ...
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CIRCUIT DESCRIPTION PWM COMPARATOR The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below the reference (VREF) or the soft start (SS) voltage. ON-TIME GENERATOR The PWM on-time duration is programmed with an external resistor ...
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CIRCUIT DESCRIPTION OVER CURRENT MONITOR The over current circuitry monitors the output current during each switching cycle. The voltage across the synchronous MOSFET, VPHASE, is monitored for over current and zero crossing. The minimum LGATE interval allows time to sample ...
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CIRCUIT DESCRIPTION COMPONENT SELECTION Selection of components for the converter is an iterative process which involves meeting the specifications and trade-offs performance and cost. The following sections will guide one through the process. Inductor Selection Inductor selection involves meeting the ...
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Output Capacitor Selection Selection of the output capacitor requires meeting voltage overshoot requirements during load removal, and meeting steady state output ripple voltage requirements. The output capacitor is the most expensive converter increases the overall system cost. The output capacitor ...
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DESIGN EXAMPLE Design Criteria: Input Voltage, VIN 16V Output Voltage, VOUT = 1.05V Switching Frequency 300KHz Inductor Ripple Current, 2Δ Maximum Output Current, IOUT = 12A Over Current Trip, IOC = 18A Overshoot ...
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LAYOUT RECOMMENDATION Bypass Capacitor: One 1µF high quality ceramic capacitor should be placed as near VCC pin as possible. The other end of capacitor can be connected to a via or connected directly to GND plane. Use a GND plane ...
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PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to ...
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Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should ...
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Stencil Design The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on ...
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MILIMITERS DIM MIN MAX A 0 0.05 b 0.375 0.475 b1 0.25 0.35 c 0.203 REF. D 5.000 BASIC E 6.000 BASIC e 1.033 BASIC e1 0.650 BASIC e2 0.852 BASIC IR WORLD HEADQUARTERS: INCHES MIN MAX ...