LM5005MH/NOPB National Semiconductor, LM5005MH/NOPB Datasheet - Page 16

• Manufacturer Part Number: LM5005MH/NOPB
• Description: IC BUCK SYNC ADJ 2.5A 20TSSOP
• Manufacturer: National Semiconductor
• Type: Step-Down (Buck)r

Specifications of LM5005MH/NOPB

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 70 V
• Current - Output: 2.5A
• Frequency - Switching: 500kHz
• Voltage - Input: 7 ~ 75 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Power - Output: 3.5W
• Dc To Dc Converter Type: Inverting/Step Down
• Pin Count: 20
• Input Voltage: 75V
• Output Voltage: 1.225 to 70V
• Switching Freq: 50 TO 500KHz
• Output Current: 2.5A
• Efficiency: 90%
• Package Type: TSSOP EP
• Output Type: Adjustable
• Switching Regulator: Yes
• Mounting: Surface Mount
• Input Voltage (min): 7V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• For Use With: LM5005EVAL - BOARD EVALUATION LM5005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM5005MH; *LM5005MH/NOPB; LM5005MH

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Components R4 and C5 configure the error amplifier as a type
II configuration which has a pole at unity and a zero at f
(2πR4C5). The error amplifier zero cancels the modulator
pole leaving a single pole response at the crossover frequen-
cy of the loop gain. A single pole response at the crossover
frequency yields a very stable loop with 90 degrees of phase
margin.
For the design example, a target loop bandwidth (crossover
frequency) of 20 kHz was selected. The compensation net-
work zero (f
tude less than the target crossover frequency. This constrains
the product of R4 and C5 for a desired compensation network
zero (1 / (2π R4 C5) to be less than 2kHz. Increasing R4 while
proportionally decreasing C5, increases the error amp gain.
Conversely, decreasing R4 while proportionally increasing
C5, decreases the error amp gain. For the design example
C5 was selected for 0.01µF and R4 was selected for 49.9
kΩ. These values configure the compensation network zero
at 320 Hz. The error amp gain at frequencies greater than f
is: R4 / R5, which is approximately 10 (20dB).
The overall loop can be predicted as the sum (in dB) of the
modulator gain and the error amp gain.
FIGURE 10. Error Amplifier Gain and Phase
Z
) should be selected at least an order of magni-
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Z
= 1 /
Z
16
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If a network analyzer is not
available, the error amplifier compensation components can
be designed with the guidelines given. Step load transient
tests can be performed to verify acceptable performance. The
step load goal is minimum overshoot with a damped re-
sponse. C6 can be added to the compensation network to
decrease noise susceptibility of the error amplifier. The value
of C6 must be sufficiently small since the addition of this ca-
pacitor adds a pole in the error amplifier transfer function. This
pole must be well beyond the loop crossover frequency. A
good approximation of the location of the pole added by C6
is: f
error amplifer noise susceptibility is to connect a capacitor
from the COMP pin to the AGND pin. When using this method
the value of the capacitor should not exceed 100pF.
BIAS POWER DISSIPATION REDUCTION
Buck regulators operating with high input voltage can dissi-
pate an appreciable amount of power for the bias of the IC.
The V
nominal V
V
the Vcc regulator. There are several techniques that can sig-
nificantly reduce this bias regulator power dissipation. Figure
12 and Figure 13 depict two methods to bias the IC from the
output voltage. In each case the internal Vcc regulator is used
to initially bias the VCC pin. After the output voltage is estab-
lished, the VCC pin potential is raised above the nominal 7V
regulation level, which effectively disables the internal V
regulator. The voltage applied to the VCC pin should never
exceed 14V. The V
V
CC
IN
p2
voltage.
regulator translates into a large power dissipation within
= fz x C5 / C6. An alternative method to decrease the
CC
FIGURE 11. Overall Loop Gain and Phase
regulator must step-down the input voltage V
CC
level of 7V. The large voltage drop across the
CC
voltage should never be larger than the
20161917
IN
to a
CC