AP2011SL-13 Diodes Inc, AP2011SL-13 Datasheet - Page 7

• Manufacturer Part Number: AP2011SL-13
• Description: IC CTLR PWM BUCK W/VFC 14-SOIC
• Manufacturer: Diodes Inc
• Type: Step-Down (Buck)r

Specifications of AP2011SL-13

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Current - Output: 3A
• Frequency - Switching: 200kHz
• Voltage - Input: 10 ~ 40 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Switching Frequency: 200 KHz
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Duty Cycle (max): 0 % to 100 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: AP2011SLDITR

Synchronous PWM with VFC Controller
Synchronous Buck Converter
Primary V
voltage-mode
controller. This section has all the features required
to build a high efficiency synchronous buck converter,
including soft-start, shutdown, and cycle-by-cycle
current limit.
Referring to the functional block diagram FIG 1, the
output voltage of the synchronous converter is set
and controlled by the output of the error comparator.
The external resistive divider reference voltage, is
derived from an internal trimmed-bandgap voltage
reference.
comparator receives its voltage from the FB pin.
The internal oscillator uses an on-chip capacitor and
trimmed precision current sources to set the virtual
oscillation
frequency oscillator sets the PWM latch. This pulls
DRVN low, turning off the low-side N_MOSFET and
DRVP is pulled low, turning on the high-side
P-MOSFET (once the cross-current control allows it).
The triangular voltage ramp at the FB pin is then
compared against the reference voltage at the
inverting input of the error comparator. When the FB
voltage increases above the reference voltage, the
comparator output goes high. This pulls DRVP high,
turning off the high-side P-MOSFET, and DRVN is
pulled high, turning on the low-side N-MOSFET
(once the cross-current control allows it). The Virtual
Frequency Oscillator then generates a programmed
off time to allow the FB voltage to return to the valley
voltage of the triangular ramp. At the end of the off
time the PWM latch is set and the cycle repeats
again.
Anachip Corp
www.anachip.com.tw
Function Description
Not Recommended for New Designs
CORE
frequency
The
power is provided by a synchronous,
pulse
inverting
width
to
200Khz.
input
modulated
of
The
the
(PWM)
virtual
error
7/9
Under Voltage Lockout
The under voltage lockout circuit of the AP2011
assures that the high-side P-MOSFET driver outputs
remain in the off state whenever the supply voltage
drops below set parameters. Lockout occurs if V
R
The current limit threshold is set by connecting an
external resistor from the V
voltage drop across this resistor is due to the 70uA
internal sink sets the voltage at the pin. This voltage
is compared to the voltage at the PHASE node. This
comparison is made only when the high-side drive is
high to avoid false current limit triggering due to
uncontributing measurements from the MOSFETs
off-voltage. When the voltage at PHASE is less than
the voltage at OCSET, an overcurrent condition
occurs and the soft start cycle is initiated. The
synchronous switch turns on and SS/ SHDN starts
starts to source 10uA and a new cycle begins. When
the soft start voltage is below 0.9V the cycle is
controlled with pulse by pulse current limiting.
Soft Start
Initially, SS/ SHDN sources 10uA of current to charge
an external capacitor. The inverting input of the error
comparator is clamped to a voltage proportional to
the voltage on SS/ SHDN . This limits the on-time of
the high-side P-MOSFET, thus leading to a
controlled ramp-up of the output voltages.
falls below 6.5V. Normal operation resumes once
V
to sink 2uA. When SS/ SHDN reaches 0.2V, it then
CC
DS(ON)
rises above 6.8V.
Current Limiting
CC
supply to OCSET. The
AP2011
Rev. 1.1 Apr 1, 2005
CC