NCP1587DR2G ON Semiconductor, NCP1587DR2G Datasheet - Page 7

• Manufacturer Part Number: NCP1587DR2G
• Description: IC CTLR SYNC BUCK LV 8-SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of NCP1587DR2G

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Current - Output: 1A
• Frequency - Switching: 275kHz
• Voltage - Input: 4.5 ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Topology: Boost, Buck
• Output Voltage: 0.8 V to 5 V
• Output Current: 8 mA
• Switching Frequency: 300 KHz
• Duty Cycle (max): 80 %
• Operating Supply Voltage: 15 V
• Supply Current: 8 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Synchronous Pin: No
• Number Of Pwm Outputs: 2
• On/off Pin: Yes
• Adjustable Output: Yes
• Switching Freq: 300KHz
• Duty Cycle: 80%
• Operating Supply Voltage (max): 13.2V
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

UVLO
unexpected behavior does not occur when V
support the internal rails and power the converter. For the
NCP1587/A, the UVLO is set to permit operation when
converting from a 5.0 input voltage.
Overcurrent Threshold Setting
Threshold ranging from 50 mV to 550 mV, simply by adding
a resistor (RSET) between BG and GND. During a short
period of time following V
an internal 10 mA current (I
determining a voltage drop across R
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is about 6 ms. Connecting a R
between BG and GND, the programmed threshold will be:
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ±25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
Current Limit Protection
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The low−side R
the end of each of the LS−FET turn−on duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
When the counter completes, the PWM logic and both
HS−FET and LS−FET are turned off. The controller has to
Undervoltage Lockout (UVLO) is provided to ensure that
NCP1587/A can easily program an Overcurrent
RSET values range from 5 kW to 55 kW. In case R
In case of a short circuit or overload, the low−side (LS)
I OCth +
I OCSET @ R OCSET
CC
OCSET
R DS(on)
DS(on)
rising over UVLO threshold,
) is sourced from BG pin,
sense is implemented at
OCSET
CC
OCSET
. This voltage
is too low to
resistor
(eq. 1)
http://onsemi.com
OCSET
7
go through a Power On Reset (POR) cycle to reset the OCP
fault.
Drivers
switch external N−channel MOSFETs. This allows the
devices to address high−power as well as low−power
conversion requirements. The gate drivers also include
adaptive non−overlap circuitry. The non−overlap circuitry
increase efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.
drive circuitry used in the chip is shown in Figure 9.
required, to realize the full benefit of the onboard drivers.
The capacitors between V
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
The NCP1587 and NCP1587A include gate drivers to
A detailed block diagram of the non−overlap and gate
Careful selection and layout of external components is
FAULT
FAULT
Figure 9. Block Diagram
+
-
+
-
2 V
CC
and GND and between BST
V
CC
1
2
8
4
3
BST
TG
PHASE
BG
GND
R
set