KSZ8995XA Micrel Inc, KSZ8995XA Datasheet

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KS8995XA General Description The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different ...

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... Hotel/campus/MxU gateway • Enterprise VoIP gateway/phone • FTTx customer premise equipment • Media converter Ordering Information Part Number Temp. Range KS8995XA 0°C to +70°C 128-Pin PQFP KSZ8995XA 0°C to +70°C 128-Pin PQFP 2 Micrel, Inc. Package Lead Finish Standard Pb-Free May 2005 ...

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KS8995XA Revision History Revision Date Summary of Changes 2.0 10/15/03 Created. 2.1 4/1/04 Editorial changes on TTL input and output electrical characteristics. 2.2 1/19/05 Insert recommeneded reset circuit. 2.3 4/13/05 Switched pins names for pins 7 & page ...

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KS8995XA Table of Contents System Level Applications .............................................................................................................................................................. 6 Pin Description (by Number) ........................................................................................................................................................... 8 Pin Description (by Name) ............................................................................................................................................................ 13 Pin Configuration ........................................................................................................................................................................... 18 Introduction ............................................................................................................................................................................ 19 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19 100BASE-TX Transmit ............................................................................................................................................................ 19 100BASE-TX ...

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KS8995XA Register 8 (0x08): Global Control 6 ................................................................................................................................ 32 Register 9 (0x09): Global Control 7 ................................................................................................................................ 32 Register 10 (0x0A): Global Control 8 ............................................................................................................................. 32 Register 11 (0x0B): Global Control 9 ............................................................................................................................. 33 Port Registers .......................................................................................................................................................................... 33 Register 16 (0x10): ...

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KS8995XA System Level Applications CPU WAN PHY & AFE (XDSL, CM...) M9999-051305 10/100 10/100 PHY 1 MAC 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 MAC 3 PHY 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 ...

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KS8995XA May 2005 10/100 10/100 MAC 1 PHY 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 PHY 5 EEPROM I/F KS8995XA Figure 3. Standalone Switch ...

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KS8995XA Pin Description (by Number) Pin Number Pin Name Type 1 MDI-XDIS 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXP2 14 ...

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KS8995XA Pin Number Pin Name Type 31 VDDAR 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd 45 NC ...

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KS8995XA Pin Number Pin Name Type 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD ...

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KS8995XA Pin Number Pin Name Type 86 SCONF1 87 SCONF0 88 GNDD Gnd 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 Ipu/O 95 LED4-0 Ipu/O 96 LED3-2 Ipu/O 97 LED3-1 Ipu/O 98 ...

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KS8995XA Pin Number Pin Name Type 109 Reserved 110 SCL 111 SDA 112 Reserved 113 PS1 114 PS0 115 RST_N 116 GNDD Gnd 117 VDDC 118 TESTEN 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA Gnd ...

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KS8995XA Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 2 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 16 GNDA Gnd 21 GNDA Gnd 27 GNDA Gnd 30 GNDA Gnd 34 GNDA Gnd 40 GNDA ...

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KS8995XA Pin Number Pin Name Type 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO Ipu MUX1 MUX2 ...

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KS8995XA Pin Number Pin Name Type 47 PWRDN_N 48 RESERVE/NC 109 Reserved 112 Reserved 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 4 RXP1 10 RXP2 19 RXP3 25 RXP4 32 RXP5 119 SCANEN 110 SCL ...

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KS8995XA Pin Number Pin Name Type 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER 1 MDIXDIS 128 TEST2 118 TESTEN 7 TXP1 ...

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KS8995XA Pin Number Pin Name Type 9 VDDAT 18 VDDAT 24 VDDAT 37 VDDAT 50 VDDC 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note Power supply Input. O ...

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KS8995XA Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 M9999-051305 128-Pin PQFP (PQ) 18 Micrel, Inc. 65 PMRXD1 ...

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KS8995XA Introduction The KS8995XA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 switch. The device runs in three modes. The first mode five-port integrated switch. The second ...

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KS8995XA 100BASE-FX Signal Detection The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V.The fiber module interface should be set by a voltage divider such that FXSDx ...

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KS8995XA Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995XA is guaranteed to learn 1K addresses and distinguishes itself from ...

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KS8995XA Media Access Controller (MAC) Operation The KS8995XA strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current ...

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KS8995XA Broadcast Storm Protection The KS8995XA has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources ...

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KS8995XA PHY Mode Connection External KS8995XA MAC Signal MTXEN SMTXEN MTXER SMTXER MTXD3 SMTXD[3] MTXD2 SMTXD[2] MTXD1 SMTXD[1] MTXD0 SMTXD[0] MTXC SMTXC MCOL SCOL MCRS SCRS MRXDV SMRXDV MRXER Not used MRXD3 SMRXD[3] MRXD2 SMRXD[2] MRXD1 SMRXD[1] MRXD0 SMRXD[0] MRXC ...

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KS8995XA SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for ...

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KS8995XA The KS8995XA can classify tagged packets using the 802.1p tag-based priority. In this prioritization scheme, the user can enable the 802.1p classification on a per port basis in bit 5 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ...

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KS8995XA DiffServ Field (Binary) 000000 000001 000010 000011 000100 • • • 111011 111100 111101 111110 111111 Once classification of the packets has been determined either by port-based priority, 802.1p tag-based priority or DiffServ priority, they are placed in either ...

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KS8995XA Configuration Interface The KS8995XA functions as a unmanaged switch EEPROM exists, the KS8995XA will operate from its default and strap- in settings. I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995XA can perform more ...

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KS8995XA Register Map Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F ...

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KS8995XA Address Name Register 2 (0x02): Global Control 0 (continued) 2 Buffer share mode 1 UNH mode 0 Link change age Register 3 (0x03): Global Control 1 7 Pass all frames 6 Reserved 5 IEEE 802.3x transmit flow control disable ...

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KS8995XA Address Name Register 4 (0x04): Global Control 2 7 Reserved 6 Multicast storm protection disable 5 Reserved 4 Flow control and back pressure fair mode 3 No excessive collision drop 2 Huge packet support 1 Legal maximum packet size ...

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KS8995XA Address Name Register 5 (0x05): Global Control 3 (continued) 1 Reserved 0 Sniff mode select Register 6 (0x06): Global Control 4 7 Switch MII back pressure enable 6 Switch MII half duplex mode 5 Switch MII flow control enable ...

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KS8995XA Address Name Register 11 (0x0B): Global Control 9 7-4 Reserved 3 PHY power save 2 Factory setting 1 LED mode 0 Reserved Port Registers The following registers are used to enable features that are assigned on a per port ...

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KS8995XA Address Name 1 Tag removal 0 Priority enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): ...

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KS8995XA Address Name 3 Back pressure enable 2 Transmit enable 1 Receive enable 0 Learning disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): ...

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KS8995XA Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): Port 5 Control 7 Address Name 7-4 Transmit ...

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KS8995XA Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 Address Name 7 Receive ...

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KS8995XA Address Name 5 Forced duplex 4 Advertised flow control capability 3 Advertised 100BT full-duplex capability 2 Advertised 100BT half-duplex capability 1 Advertised 10BT full-duplex capability 0 Advertised 10BT half-duplex capability Register 29 (0x1D): Port 1 Control 13 Register 45 ...

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KS8995XA Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 Address Name 7 MDIX status 6 AN done 5 Link good ...

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KS8995XA Address Name Register 97 (0x61): TOS Priority Control Register 1 7-0 DSCP[55:48] Register 98 (0x62): TOS Priority Control Register 2 7-0 DSCP[47:40] Register 99 (0x63): TOS Priority Control Register 3 7-0 DSCP[39:32] Register 100 (0x64): TOS Priority Control Register ...

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KS8995XA Address Name 9 Restart AN 8 Force full-duplex 7 Collision test 6 Reserved 5 Reserved 4 Force MDI 3 Disable auto MDIX 2 Disable far end fault 1 Disable transmit 0 Disable LED Register 1: MII Status 15 T4 ...

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KS8995XA Address Name 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Selector field Register 5: Link Partner Ability 15 Next page 14 LP ACK 13 Remote fault ...

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KS8995XA Absolute Maximum Ratings Supply Voltage ( ............................. –0.5V to +2.4V DDAR, DDAP, DDC ( ........................................ –0.5V to +4.0V DDAT, DDIO Input Voltage (All Inputs) ............................. –0.5V to +4.0V Output Voltage (All Outputs) ....................... –0.5V ...

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KS8995XA Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of I SET SET Output Jitters 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential ...

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KS8995XA Timing Diagrams Receive Timing SCL SDA Figure 11. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 12. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time ...

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KS8995XA Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-051305 ts2 tcyc2 th2 Figure 13. SNI Input Timing tcyc2 ...

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KS8995XA Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 15. MAC Mode MII Timing – Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 16. MAC Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) ...

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KS8995XA Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 17. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 18. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) ...

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KS8995XA Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC Reset Circuit Diagram ...

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KS8995XA Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...

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... KS8995XA Package Information MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...