KSZ8993MI Micrel Inc, KSZ8993MI Datasheet - Page 2

• Manufacturer Part Number: KSZ8993MI
• Description: IC SWITCH 10/100 W/TXRX 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8993MI

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2124; KSZ8993MI

Features
• Proven Integrated 3-Port 10/100 Ethernet Switch
• Comprehensive Configuration Register Access
Micrel, Inc.
October 2008
– 2nd generation switch with three MACs and two
PHYs fully compliant to IEEE 802.3u standard
– Non-blocking switch fabric assures fast packet
delivery by utilizing a 1K MAC address lookup table
and a store-and-forward architecture
– Full duplex IEEE 802.3x flow control (pause) with
force mode option
– Half-duplex back pressure flow control
– Automatic MDI/MDI-X crossover with disable and
enable option
– 100BASE-FX support on port 1
– MII interface supports both MAC mode and PHY
mode
– 7-wire serial network interface (SNI) support for
– Comprehensive LED Indicator support for link,
activity, full/half duplex and 10/100 speed
– Serial management interface (SMI) to all internal
registers
– MII management (MIIM) interface to PHY registers
– SPI and I
– I/0 Pins strapping and EEPROM to program
selective registers in unmanaged switch mode
legacy MAC
P1 LED[3:0]
P2 LED[3:0]
MDI/MDI-X
MDI/MDI-X
2
C Interface to all internal registers
MII/SNI
AUTO
AUTO
MIIM
SMI
SPI
I 2 C
T/TX/FX
10/100
10/100
PHY 1
PHY 2
T/TX
Drivers
LED
Registers
Control
10/100
10/100
10/100
MAC3
2
MAC1
MAC2
SNI
SPI
• QoS/CoS Packet Prioritization Support
• Advanced Switch Features
– Upstream special tagging mode to inform the
processor which ingress port receives the packet
– Control registers configurable on the fly (port-
priority, 802.1p/d/q, AN…)
– Per port, 802.1p and DiffServ-based
– Re-mapping of 802.1p priority field per port basis
– IEEE 802.1q VLAN support for up to 16 groups
(full-range of VLAN ID)
– VLAN ID tag/untag options, per port basis
– IEEE 802.1p/q tag insertion or removal on a per
port basis (egress)
– Programmable rate limiting from 0Mbps to
100Mbps at the ingress and egress port, rate options
for high and low priority per port basis
– Broadcast storm protection with % control (global
and per port basis)
– IEEE 802.1d spanning tree protocol support
– IGMP v1/v2 snooping support for multicast packet
filtering
– Double-tagging support
Configuration Pins
Strap-In
Manageme nt
Manageme nt
1KLook-Up
Counters
EEP ROM
Interface
Engine
Queue
Buffers
Buffer
Frame
MIB
M9999-020606
KSZ8993M/ML