KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 29

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

KS8695PX
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Note:
1. I = Input.
M9999-091605
O = Output.
I/O = Bidirectional.
P10
P10
P10
R10
R10
R10
U10
U10
U10
R11
R11
R11
U11
U11
U11
P12
P12
P12
R12
R12
R12
U12
U12
U12
P13
P13
P13
R13
R13
R13
U13
U13
U13
P14
P14
P14
R14
R14
R14
U14
U14
U14
U15
U15
U15
U16
U16
U16
U16
U16
R16
R16
R16
R16
R16
P16
P16
P16
P16
P16
R15
R15
R15
R15
R15
P15
P15
P15
P15
P15
T10
T10
T10
P11
P11
P11
T11
T11
T11
T12
T12
T12
T13
T13
T13
T14
T14
T14
T15
T15
T15
T16
T16
T16
T16
T16
Pin
Pin
Pin
Pin
P7
P7
P7
P7
P7
R7
R7
R7
R7
R7
P8
P8
P8
P8
P8
R8
R8
R8
U8
U8
U8
P9
P9
P9
P9
P9
R9
R9
R9
U9
U9
U9
R4
R4
R4
R4
R4
P5
P5
P5
P5
P5
R5
R5
R5
R5
R5
U5
U5
U5
U5
U5
P6
P6
P6
P6
P6
R6
R6
R6
R6
R6
U6
U6
U6
U6
U6
T8
T8
T8
T9
T9
T9
T5
T5
T5
T5
T5
T6
T6
T6
T6
T6
SDCSN[1]
SDCSN[1]
SDCSN[1]
SDCSN[1]
SDCSN[1]
SDCSN[0]
SDCSN[0]
SDCSN[0]
SDCSN[0]
SDCSN[0]
DATA[31]
DATA[31]
DATA[31]
DATA[31]
DATA[31]
DATA[30]
DATA[30]
DATA[30]
DATA[30]
DATA[30]
DATA[29]
DATA[29]
DATA[29]
DATA[29]
DATA[29]
DATA[28]
DATA[28]
DATA[28]
DATA[27]
DATA[27]
DATA[27]
DATA[26]
DATA[26]
DATA[26]
DATA[25]
DATA[25]
DATA[25]
DATA[25]
DATA[25]
DATA[24]
DATA[24]
DATA[24]
DATA[23]
DATA[23]
DATA[23]
DATA[22]
DATA[22]
DATA[22]
DATA[21]
DATA[21]
DATA[21]
DATA[20]
DATA[20]
DATA[20]
DATA[19]
DATA[19]
DATA[19]
DATA[18]
DATA[18]
DATA[18]
DATA[17]
DATA[17]
DATA[17]
DATA[16]
DATA[16]
DATA[16]
DATA[15]
DATA[15]
DATA[15]
DATA[14]
DATA[14]
DATA[14]
DATA[13]
DATA[13]
DATA[13]
DATA[12]
DATA[12]
DATA[12]
DATA[11]
DATA[11]
DATA[11]
DATA[10]
DATA[10]
DATA[10]
SDRASN
SDRASN
SDRASN
SDRASN
SDRASN
SDCASN
SDCASN
SDCASN
SDCASN
SDCASN
SDQM[3]
SDQM[3]
SDQM[3]
SDQM[3]
SDQM[3]
SDQM[2]
SDQM[2]
SDQM[2]
SDQM[2]
SDQM[2]
SDQM[1]
SDQM[1]
SDQM[1]
SDQM[1]
SDQM[1]
SDQM[0]
SDQM[0]
SDQM[0]
SDQM[0]
SDQM[0]
ECSN[2]
ECSN[2]
ECSN[2]
ECSN[2]
ECSN[2]
ECSN[1]
ECSN[1]
ECSN[1]
ECSN[1]
ECSN[1]
ECSN[0]
ECSN[0]
ECSN[0]
ECSN[0]
ECSN[0]
EWAITN
EWAITN
EWAITN
EWAITN
EWAITN
RCSN[1]
RCSN[1]
RCSN[1]
RCSN[1]
RCSN[1]
RCSN[0]
RCSN[0]
RCSN[0]
RCSN[0]
RCSN[0]
SDWEN
SDWEN
SDWEN
SDWEN
SDWEN
DATA[9]
DATA[9]
DATA[9]
DATA[8]
DATA[8]
DATA[8]
DATA[7]
DATA[7]
DATA[7]
DATA[6]
DATA[6]
DATA[6]
DATA[5]
DATA[5]
DATA[5]
DATA[4]
DATA[4]
DATA[4]
DATA[3]
DATA[3]
DATA[3]
DATA[2]
DATA[2]
DATA[2]
DATA[1]
DATA[1]
DATA[1]
DATA[0]
DATA[0]
DATA[0]
Name
Name
Name
Name
I/O Type
I/O Type
I/O Type
I/O Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
(1)
Description
Description
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695PX
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695PX
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695PX
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695PX
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695PX
also supports 8-bit and 16-bit data bus widths.
also supports 8-bit and 16-bit data bus widths.
also supports 8-bit and 16-bit data bus widths.
also supports 8-bit and 16-bit data bus widths.
also supports 8-bit and 16-bit data bus widths.
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695PX
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695PX
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695PX
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695PX
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695PX
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM.
SDRAM.
SDRAM.
SDRAM.
SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDQM is sampled high and is an output mask signal for write accesses and an
SDQM is sampled high and is an output mask signal for write accesses and an
SDQM is sampled high and is an output mask signal for write accesses and an
SDQM is sampled high and is an output mask signal for write accesses and an
SDQM is sampled high and is an output mask signal for write accesses and an
output enable signal for read accesses. Input data are masked during a write cycle.
output enable signal for read accesses. Input data are masked during a write cycle.
output enable signal for read accesses. Input data are masked during a write cycle.
output enable signal for read accesses. Input data are masked during a write cycle.
output enable signal for read accesses. Input data are masked during a write cycle.
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
DATA[31:24], respectively.
DATA[31:24], respectively.
DATA[31:24], respectively.
DATA[31:24], respectively.
DATA[31:24], respectively.
External I/O Device Chip Select: Active low. Three external I/O banks are provided
External I/O Device Chip Select: Active low. Three external I/O banks are provided
External I/O Device Chip Select: Active low. Three external I/O banks are provided
External I/O Device Chip Select: Active low. Three external I/O banks are provided
External I/O Device Chip Select: Active low. Three external I/O banks are provided
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
The ECSNx signals indicate which of the three I/O banks is selected.
The ECSNx signals indicate which of the three I/O banks is selected.
The ECSNx signals indicate which of the three I/O banks is selected.
The ECSNx signals indicate which of the three I/O banks is selected.
The ECSNx signals indicate which of the three I/O banks is selected.
External Wait: Active low. This signal is asserted when an external I/O device or a
External Wait: Active low. This signal is asserted when an external I/O device or a
External Wait: Active low. This signal is asserted when an external I/O device or a
External Wait: Active low. This signal is asserted when an external I/O device or a
External Wait: Active low. This signal is asserted when an external I/O device or a
ROM/SRAM/FLASH bank needs more access cycles than those defi ned in the
ROM/SRAM/FLASH bank needs more access cycles than those defi ned in the
ROM/SRAM/FLASH bank needs more access cycles than those defi ned in the
ROM/SRAM/FLASH bank needs more access cycles than those defi ned in the
ROM/SRAM/FLASH bank needs more access cycles than those defi ned in the
corresponding control register.
corresponding control register.
corresponding control register.
corresponding control register.
corresponding control register.
ROM/SRAM/FLASH Chip Select: Active low. The KS8695PX can access up to two
ROM/SRAM/FLASH Chip Select: Active low. The KS8695PX can access up to two
ROM/SRAM/FLASH Chip Select: Active low. The KS8695PX can access up to two
ROM/SRAM/FLASH Chip Select: Active low. The KS8695PX can access up to two
ROM/SRAM/FLASH Chip Select: Active low. The KS8695PX can access up to two
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
map the CPU addresses into physical memory banks.
map the CPU addresses into physical memory banks.
map the CPU addresses into physical memory banks.
map the CPU addresses into physical memory banks.
29
September 2005
Micrel