LM8342SDX/NOPB National Semiconductor, LM8342SDX/NOPB Datasheet - Page 10

• Manufacturer Part Number: LM8342SDX/NOPB
• Description: IC PROG TFT CALIBRATOR 10-LLP
• Manufacturer: National Semiconductor

Specifications of LM8342SDX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM8342SDX

www.national.com
The maximum output current of the LM8342 can be defined
using an external resistor R
reference voltage AV
culated using Equation 1.
The operating range for the output current is given in the
Electrical Characteristics table on page 2. Variations of the
voltage reference AV
this output current. Using a resistor with a low temperature
coefficient is recommended.
The relative value of I
can be controlled digitally in 128 steps, using the internal
DAC. This results in an output current described by Equation
2.
Using the serial interface bus the operator can store the DAC
value in the LM8342s 7-bits volatile register temporarily, or
permanent in the EEPROM. During a start-up sequence the
LM8342 will copy the contents of the EEPROM to the register
setting the DC value.
CONTROLLING THE DEVICE
The LM8342s current sink can be programmed using a serial
interface bus. Additional functions (e.g. storing data in the
EEPROM) can be controlled in combination with external in-
puts. Table 1 shows the pins of the LM8342 and gives a short
functional description.
SDA & SCL
(Serial interface
bus)
AV
V
SET
OUT
SCL-S
DD
DD
Pin name
TABLE 1. Pin Descriptions
The LM8342 output current can be
controlled using the serial I
interface. This 2-Wire interface uses a
clock and a data signal. New values can
be written to the memory, or the current
value can be read back from the device.
The I
in more detail in the next chapter.
Analog reference voltage for the DAC.
Supply voltage for both the analog and
digital circuitry.
An external resistor R
SET pin determines the maximum output
current, see Equation 1.
The output of the programmable current
sink.
For in-circuit PCB testing, the LM8342 can
use the additional Switched SCL signal
(SCL-S) input for applying the SCL clock
signal.
DD
OUT
DD
or the external resistor R
2
. This maximum current can be cal-
C compatible interface is discussed
with respect to the maximum current
SET
in combination with an analog
Function
SET
connected to the
2
C compatible
SET
will affect
(1)
(2)
10
I
The LM8342 supports an I
tocol, which is a bidirectional bus oriented communication
protocol. Any device that sends data on the bus is defined as
a transmitter and the receiving device as a receiver. The I
compatible communication protocol uses 2 wires: SDA (Serial
Data Line) and SCL (Serial Clock Line). For both lines an ex-
ternal pull-up resistor, connected to the supply voltage, is
required. The device controlling the bus is known as the mas-
ter, and the device or devices being controlled are the slaves.
Each device has its own specific address. The address of the
LM8342 is 9E
and provides the clock. The LM8342 always operates as a
slave. A typical system using an I
is given in Figure 5.
The LM8342 can be used in an I
specifications of the LM8342, dealing with the interface bus,
are guaranteed by design. Except for the bus speed, which is
specified in the Electrical Characteristics table.
KEY ASPECT OF I
In this section a brief overview is presented, discussing the
key aspect of I
the timing aspects of the I
WP
WP
2
C SERIAL INTERFACE BUS
Pin name
N
P
FIGURE 5. System Using an I
2
HEX
C compatible communication. Figure 6 shows
. The master initiates the communication
“Write Protect Not” (Input) has 2 functions:
1. Prohibits programming the EEPROM,
when low or left floating (Internal a pull-
down resistor is connected) When WP
set to a low level, only the volatile register
is accessible. If WP
also the EEPROM is accessible. Actual
writing to the EEPROM or the register is
done using the “P-bit” in the serial
communication.
2. WP
When WP
connected to SCL. The operator should
turn off the original SCL clock.
Write Protect Signal (Output). This is the
inverted WP
2
C COMPATIBLE COMMUNICATION
N
2
2
switches the SCL-S clock line.
C compatible serial interface.
C compatible communication pro-
N
is set to a high level SCL-S is
N
signal.
2
C compatible interface bus
2
Function
C compatible system. All
2
C compatible Bus
N
is set to a high level
20139231
N
2
is
C