KS8993M Micrel Inc, KS8993M Datasheet - Page 52

• Manufacturer Part Number: KS8993M
• Description: IC SWITCH 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993M

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1013 - BOARD EVAL EXPERIMENT KS8993M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Register 6 (0x06): Global Control 4 (continued)
Bit
3
2-0
Register 7 (0x07): Global Control 5
Bit
7-0
Note: Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Register 8 (0x08): Global Control 6
Bit
7-0
Register 9 (0x09): Global Control 7
Bit
7-0
Register 10 (0x0A): Global Control 8
Bit
7-0
Register 11 (0x0B): Global Control 9
Bit
7
6
5
4
3
Micrel, Inc.
April 2005
Name
Null VID
replacement
Broadcast
storm
protection rate
Bit [10:8]
Name
Broadcast
storm
protection
rate
Bit [7:0]
Name
Name
Name
Name
PHY
power
save
Factory testing
Factory testing
Factory testing
Reserved
Reserved
Reserved
Reserved
(1)
R/W
R/W
R/W
RW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
= 1, enable PHY power save mode
= 0, disable PHY power save mode
Reserved
Testing mode, must be 0
Reserved
Description
= 1, will replace NULL VID with port VID(12 bits)
= 0, no replacement for NULL VID
This register along with the next register determines
how many “64 byte blocks” of packet data allowed on
an input port in a preset period. The period is 50ms
for 100BT or 500ms for 10BT. The default is 1%.
Description
This register along with the previous register
determines how many “64 byte blocks” of packet data
are allowed on an input port in a preset period. The
period is 67ms for 100BT or 500ms for 10BT. The
default is 1%.
Description
Reserved
Description
Reserved
Description
Reserved
52
Default
0
000
Default
0x63
Default
0x4E
Default
0x24
Default
0x24
Default
0
0
0
0
1
KS8993M/ML/MI
M9999-041205