KS8995M Micrel Inc, KS8995M Datasheet

IC SWITCH 10/100 5PORT 128PQFP

KS8995M

Manufacturer Part Number
KS8995M
Description
IC SWITCH 10/100 5PORT 128PQFP
Manufacturer
Micrel Inc
Datasheets

Specifications of KS8995M

Applications
*
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
5
Internal Memory Buffer Size
64
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII/SNI
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.9/2.6/3.6V
Operating Supply Voltage (min)
1.7/2.4/3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1017 - BOARD EVAL EXPERIMENT KS8995M
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant

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MICREL
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KS8995M
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Micrel Inc
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10 000
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KS8995MA
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Micrel Inc
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KS8995MA
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Part Number:
KS8995MI
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Micrel Inc
Quantity:
10 000
General Description
The KS8995M is a highly integrated Layer-2 managed switch
with optimized BOM (Bill of Materials) cost for low port count,
cost-sensitive 10/100Mbps switch systems. It also provides
an extensive feature set such as tag/port-based VLAN, QoS
(Quality of Service) priority, management, MIB counters, dual
MII interfaces and CPU control/data interfaces to effectively
address both current and emerging Fast Ethernet applica-
tions.
The KS8995M contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five MAC (Media
Access Control) units, a high-speed non-blocking switch
fabric, a dedicated address look-up engine, and an on-chip
frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,
two of the PHY units support 100BaseFX (Ports 4 and 5).
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Functional Diagram
December 2003
KS8995M
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
Control Reg I/F
MII-SW or SNI
MDC, MDI/O
LED0[5:1]
LED1[5:1]
LED2[5:1]
MDI/MDIX
MDI/MDIX
MDI/MDIX
MDI/MDIX
MDI/MDIX
Auto
Auto
MII-P5
Auto
Auto
Auto
T/Tx/Fx 4
T/Tx/Fx 5
LED I/F
10/100
10/100
10/100
10/100
10/100
T/Tx 1
T/Tx 2
T/Tx 3
Registers
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
Control
10/100
MAC 4
10/100
MAC 5
1
SNI
SPI
Features
• Integrated switch with five MACs and five Fast Ethernet
• Shared memory based switch fabric with fully non-
• 1.4Gbps high-performance memory bandwidth
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in
• Dual MII configuration: MII-Switch (MAC or PHY mode
• IEEE 802.1q tag-based VLAN (16 VLANs, full-range
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting 0Mbps to 100Mbps, ingress
• Flow control or drop packet rate limiting (ingress port)
• Integrated MIB counters for fully compliant statistics
transceivers fully compliant to IEEE 802.3u standard
blocking configuration
Ports 4 and 5)
MII) and MII-P5 (PHY mode MII)
VID) for DMZ port, WAN/LAN separation or inter-VLAN
switch links
and egress port, rate options for high and low priority,
per-port-basis
gathering, 34 MIB counters per port
Integrated 5-Port 10/100 Managed Switch
1K look-up
KS8995M
Counters
EEPROM
Buffers
Engine
Queue
Mgmnt
Mgmnt
Frame
Buffer
KS8995M
Rev 1.12
MIB
I/F
M9999-120403
Micrel

Related parts for KS8995M

KS8995M Summary of contents

Page 1

... KS8995M General Description The KS8995M is a highly integrated Layer-2 managed switch with optimized BOM (Bill of Materials) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, QoS (Quality of Service) priority, management, MIB counters, dual ...

Page 2

... Standalone 10/100 switch • Hotel/campus/MxU gateway • Enterprise VoIP gateway/phone • FTTx customer premise equipment • Managed media converter Ordering Information Part Number Temperature Range KS8995M +70 C KSZ8995M +70 C KS8995MI – + Micrel Package 128-Pin PQFP 128-Pin PQFP Lead Free 128-Pin PQFP December 2003 ...

Page 3

... Updated table 2 for MAC mode connections. Separate static MAC bit assignments for read and write. Edited read and write examples to MAC tables and MIB counters. Changed Table 3 KS8995M signals to “S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed all port register addresses ...

Page 4

... KS8995M Table of Contents System Level Applications ......................................................................................................................................... 7 Pin Description (by Number) ...................................................................................................................................... 9 Pin Description (by Name) ........................................................................................................................................ 15 Pin Configuration ...................................................................................................................................................... 21 Introduction ........................................................................................................................................................... 22 Functional Overview: Physical Layer Transceiver ................................................................................................ 22 100BaseTX Transmit ........................................................................................................................................... 22 100BaseTX Receive ............................................................................................................................................ 22 PLL Clock Synthesizer ......................................................................................................................................... 22 Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 22 100BaseFX Operation ......................................................................................................................................... 22 100BaseFX Signal Detection ............................................................................................................................... 22 100BaseFX Far End Fault ................................................................................................................................... 23 10BaseT Transmit ............................................................................................................................................... 23 10BaseT Receive ...

Page 5

... KS8995M Register Description ................................................................................................................................................. 39 Global Registers .................................................................................................................................................. 39 Register 0 (0x00): Chip ID0 ......................................................................................................................... 39 Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39 Register 2 (0x02): Global Control 0 ............................................................................................................. 40 Register 3 (0x03): Global Control 1 ............................................................................................................. 40 Register 4 (0x04): Global Control 2 ............................................................................................................. 41 Register 5 (0x05): Global Control 3 ............................................................................................................. 42 Register 6 (0x06): Global Control 4 ............................................................................................................. 42 Register 7 (0x07): Global Control 5 ............................................................................................................. 43 Register 8 (0x08): Global Control 6 ...

Page 6

... KS8995M Register 112 (0x70): Indirect Data Register 8 ............................................................................................. 51 Register 113 (0x71): Indirect Data Register 7 ............................................................................................. 51 Register 114 (0x72): Indirect Data Register 6 ............................................................................................. 51 Register 115 (0x73): Indirect Data Register 5 ............................................................................................. 51 Register 116 (0x74): Indirect Data Register 4 ............................................................................................. 51 Register 117 (0x75): Indirect Data Register 3 ............................................................................................. 51 Register 118 (0x76): Indirect Data Register 2 ...

Page 7

... KS8995M System Level Applications CPU WAN PHY & AFE (xDSL, CM...) December 2003 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC External WAN port PHY not needed Figure 1. Broadband Gateway SPI/GPIO SPI MII-SW ...

Page 8

... KS8995M M9999-120403 10/100 10/100 MAC 1 PHY 1 10/100 10/100 PHY 2 MAC 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 PHY 5 Figure 3. Standalone Switch 8 Micrel 5-port LAN December 2003 ...

Page 9

... KS8995M Pin Description (by Number) Pin Number Pin Name Type 1 TEST1 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXM1 8 TXP1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXM2 14 TXP2 15 VDDAR 16 GNDA Gnd 17 ISET 18 VDDAT 19 RXP3 20 RXM3 21 GNDA Gnd 22 TXM3 23 TXP3 24 VDDAT 25 RXP4 26 RXM4 27 GNDA ...

Page 10

... KS8995M Pin Number Pin Name Type 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXM5 36 TXP5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd 45 MUX1 46 MUX2 47 PWRDN_N 48 RESERVE 49 GNDD Gnd 50 VDDC 51 PMTXEN 52 PMTXD3 53 PMTXD2 54 PMTXD1 55 PMTXD0 56 PMTXER 57 PMTXC 58 GNDD Gnd Note Power supply ...

Page 11

... KS8995M Pin Number Pin Name Type 59 VDDIO 60 PMRXC 61 PMRXDV Ipd/O 62 PMRXD3 Ipd/O 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD Gnd 77 VDDIO 78 SMRXC 79 SMRXDV Ipd/O 80 SMRXD3 Ipd/O 81 SMRXD2 Ipd/O Note: 1 ...

Page 12

... KS8995M Pin Number Pin Name Type 82 SMRXD1 Ipd/O 83 SMRXD0 Ipd/O 84 SCOL Ipd/O 85 SCRS Ipd/O 86 SCONF1 87 SCONF0 88 GNDD Gnd 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 Ipu/O 95 LED4-0 Ipu/O 96 LED3-2 Ipu/O 97 LED3-1 Ipu/O Note Power supply I = Input O = Output I/O = Bi-directional ...

Page 13

... I2C master mode See “pin# 113.” Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995M is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode. Ipd ...

Page 14

... KS8995M Pin Number Pin Name Type 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA Gnd 125 VDDAR 126 GNDA Gnd 127 GNDA Gnd 128 TEST2 Note Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down ...

Page 15

... KS8995M Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 124 GNDA Gnd 42 GNDA Gnd 44 GNDA Gnd 2 GNDA Gnd 16 GNDA Gnd 30 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 21 GNDA Gnd 27 GNDA Gnd 34 GNDA Gnd 40 GNDA Gnd 120 NC 127 GNDA Gnd 126 ...

Page 16

... KS8995M Pin Number Pin Name Type 97 LED3-1 Ipu/O 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO 1 TEST1 45 MUX1 46 MUX2 68 PCOL Ipd/O 67 PCRS Ipd/O 60 PMRXC 65 PMRXD0 Ipd/O 64 PMRXD1 Ipd/O 63 PMRXD2 Ipd/O 62 PMRXD3 ...

Page 17

... PHY[5] MII transmit enable Ipd 5 PHY[5] MII transmit error Ipd Serial bus configuration pin. See “pin# 113.” Ipd Serial bus configuration pin If EEPROM is not present, the KS8995M will start itself with chip default (00)... Pin Config. PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Ipu Full-chip power down ...

Page 18

... KS8995M Pin Number Pin Name Type 87 SCONF0 86 SCONF1 85 SCRS Ipd/O 78 SMRXC 83 SMRXD0 Ipd/O 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER Note Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up ...

Page 19

... See “pin# 113.” Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995M is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode connect for normal operation. Factory test pin. ...

Page 20

... KS8995M Pin Number Pin Name Type 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise ...

Page 21

... KS8995M Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 December 2003 128-Pin PQFP (PQ) 21 Micrel 65 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC ...

Page 22

... KS8995M via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995M supports IEEE 802.3 10BaseT, 100BaseTX on all ports, and 100BaseFX on ports 4 and 5. The KS8995M can be used as two separate media converters. ...

Page 23

... Power Management The KS8995M features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shut down ...

Page 24

... The KS8995M has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. ...

Page 25

... KS8995M December 2003 Start -Search VLAN table NO VLAN ID PTF1=NULL -Ingress VLAN filtering VALID? -Discard NPVID check YES Search complete. FOUND This search is based on Search Static Get PTF1 from DA or DA+FID Table static table NOT FOUND Search complete. Dynamic FOUND This search is based on ...

Page 26

... KS8995M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995M will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times ...

Page 27

... Receive error MRXER Receive data bit 3 MRXD3 Receive data bit 2 MRXD2 Receive data bit 1 MRXD1 Receive data bit 0 MRXD0 Receive clock MRXC Table 2. MII–SW Signals 27 KS8995M signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] ...

Page 28

... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995M has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995M has an MTXER pin, it should be tied low. ...

Page 29

... KS8995M will treat them as normal packets and an internal look-up will be performed. The KS8995M uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states (blocking, disable, listening, learning). The Table 5 shows the egress rules when dealing with STPID. ...

Page 30

... KS8995M Tx Port Ingress Tag Field “Tag Insertion” (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) Not Tagged Don’t care Table 5. STPID Egress Rules (Processor to Switch Port 5) For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet was received on, defined as: “ ...

Page 31

... Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “tx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to port 1 after the internal look-up. The KS8995M will forward the packet to both port 1 and port 5. ...

Page 32

... The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995M uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. ...

Page 33

... KS8995M Configuration Interface The KS8995M can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KS8995M will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # Pin Name PU/PD 1 TEST1 NC 45 ...

Page 34

... PU (default) = Aging Enable Aging disable. LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See “pin# 86 SCONF1. ” Serial bus configuration pin If EEPROM is not present, the KS8995M will start itself with chip default (00)... Pin Configuration Serial Bus Configuration ...

Page 35

... SDA To configure the KS8995M with a pre-configured EEPROM use the following steps the board level, connect pin 110 on the KS8995M to the SCL pin on the EEPROM. Connect pin 111 on the KS8995M to the SDA pin on the EEPROM. 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00”. This puts the KS8995M serial bus configuration into I2C master mode ...

Page 36

... Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure multiple read as shown in Figure 11. Note that read data is registered out of SPIQ on the falling edge of SPIC. 6. After configuration is written and verified, write a ‘1’ to register 1 bit 0 to begin KS8995M operation. M9999-120403 ...

Page 37

... KS8995M SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND December 2003 WRITE ADDRESS Figure 8. SPI Write Data Cycle READ ADDRESS Figure 9. SPI Read Data Cycle 37 Micrel WRITE DATA READ DATA M9999-120403 ...

Page 38

... The MIIM interface does not have access to all the configuration registers in the KS8995M. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other hand, can be used to access the entire KS8995M feature set. ...

Page 39

... KS8995M Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port 2 Status Registers 48-61 0x30-0x3D ...

Page 40

... KS8995M Address Name Register 2 (0x02): Global Control 0 7 Reserved 6-4 802.1p base priority 3 Enable PHY MII 2 Buffer share mode 1 UNH mode 0 Link change age Register 3 (0x03): Global Control 1 7 Pass all frames 6 Reserved 5 IEEE 802.3x Transmit flow control disable 4 IEEE 802.3x Receive ...

Page 41

... KS8995M Address Name 2 Aging enable 1 Fast age enable 0 Aggressive back off enable Register 4 (0x04): Global Control 2 7 Unicast port-VLAN mismatch discard 6 Multicast Storm protection disable 5 Back pressure mode 4 Flow control and back pressure fair mode 3 No excessive collision drop 2 Huge packet support ...

Page 42

... KS8995M Address Name 1 Legal Maximum Packet size check disable 0 Priority Buffer reserve Register 5 (0x05): Global Control 3 7 802.1q VLAN enable 6 IGMP snoop enable on Switch MII interface 5 Enable direct mode on Switch MII interface 4 Enable pre tag on Switch MII interface 3-2 Priority Scheme select 1 Enable “ ...

Page 43

... KS8995M Address Name 5 Switch MII flow control enable 4 Switch MII 10BT 3 Null VID replacement 2-0 Broadcast storm protection rate Bit [10:8] Register 7 (0x07): Global Control 5 7-0 Broadcast storm protection rate Bit [7:0] Note: 1. 148,800 frames/sec 50ms/interval frames/interval (approx.) = 0x4A Register 8 (0x08): Global Control 6 ...

Page 44

... KS8995M Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 ...

Page 45

... KS8995M Address Name 5 Transmit sniff 4-0 Port VLAN membership Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 Address Name 7 Reserved 6 Ingress VLAN filtering 5 Discard Non PVID packets 4 Force flow control ...

Page 46

... KS8995M Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address Name 7-0 Default tag [15:8] Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Port 4 Control 4 ...

Page 47

... KS8995M Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Register 72 (0x48): Port 4 Control 8 Register 88 (0x58): Port 5 Control 8 Address Name 7-0 Receive high priority rate control [7:0] Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 ...

Page 48

... KS8995M Address Name 3 High priority receive rate flow control enable 2 Transmit differential priority rate control 1 Low priority transmit rate control enable 0 High priority transmit rate control enable Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 ...

Page 49

... KS8995M Address Name 0 Advertised 10BT half-duplex capability Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 Register 93 (0x5D): Port 5 Control 13 Address Name 7 LED off 6 Txids 5 Restart AN 4 Disable Far end fault 3 Power down 2 Disable auto MDI/MDIX ...

Page 50

... KS8995M Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Register 79 (0x4F): Port 4 Status 1 Register 95 (0x5F): Port 5 Status 1 Address Name 7-1 Reserved 0 Far end fault Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit DSCP (Differentiated Services Code Point) register used to determine priority from the 6 bit TOS field in the IP header ...

Page 51

... KS8995M Address Name Register 110 (0x6E): Indirect Access Control 0 7-5 Reserved 4 Read High Write Low 3-2 Table select 1-0 Indirect address high Register 111 (0x6F): Indirect Access Control 1 7-0 Indirect address low Note: write to register 111 will actually trigger a command. Read or write access will be decided by bit 4 of reg110. ...

Page 52

... KS8995M Address Name Register 126 (0x7E): Analog Testing Control 1 7-0 Factory testing Register 127 (0x7F): Analog Testing Status 7-0 Factory testing M9999-120403 Description Reserved Reserved 52 Micrel Mode Default R/W 0x0 RO 0x0 December 2003 ...

Page 53

... The static table can only be accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by KS8995M. An external device does all addition, modification and deletion. ...

Page 54

... KS8995M Examples: (1) Static Address Table Read (read the 2nd entry) Write to reg110 with 0x10 (read static table selected) Write to reg111 with 0x1 (trigger the read operation) Then Read reg113 (60-56) Read reg114 (55-48) Read reg115 (47-40) Read reg116 (39-32) Read reg117 (31-24) ...

Page 55

... VID If 802.1q VLAN mode is enabled, KS8995M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look-up process will start from the VLAN table look-up. If the VID is not valid, the packet will be dropped and no address learning will take place ...

Page 56

... KS8995M Dynamic MAC Address This table is ready only. The contents are maintained by KS8995M only. Address Name Format of Dynamic MAC Address Table (1K entries) 68 MAC empty 67- valid entries 57-56 Time stamp 55 Data ready 54-52 Source port 51-48 FID 47-0 MAC address Examples: (1) Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size ...

Page 57

... KS8995M MIB Counters The MIB counters are provided on per port basis. The indirect memory is as below. For port 1 Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCerror 0x8 RxAlignmentError 0x9 RxControl8808Pkts ...

Page 58

... KS8995M For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, same offset definition (ox80-0x9f) Address Name Format of Per Port MIB Counters (16 entries) ...

Page 59

... KS8995M (2) MIB counter read (read port counter) Write to reg110 with 0x1c (read MIB counter selected) Write to reg111 with 0x2e (trigger the read operation ) Then Read reg117 (counter value 31-24 bit there was a counter overflow bit restart (reread) from this register. Read reg118 (counter value 23-16) ...

Page 60

... KS8995M MIIM Registers (All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI). The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, “ ...

Page 61

... KS8995M Address Name Register 1: MII Status 15 T4 capable 14 100 Full capable 13 100 Half capable 12 10 Full capable 11 10 Half capable 10-7 Reserved 6 Preamble suppressed 5 AN complete 4 Far end fault 3 AN capable 2 Link status 1 Jabber test 0 Extended capable Register 2: PHYID HIGH 15-0 ...

Page 62

... KS8995M Address Name Register 5: Link Partner Ability 15 Next page 14 LP ACK 13 Remote fault 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Reserved M9999-120403 Description NOT SUPPORTED NOT SUPPORTED NOT SUPPORTED Link partner pause capability ...

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... KS8995M Absolute Maximum Ratings Supply Voltage ( ................. –0.5V to +2.4V DDAR, DDAP, DDC DDAT (V ) .................................................... –0.5V to +4.0V DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ............................................ –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270 C Storage Temperature (T ) ....................... – +150 C S Electrical Characteristics V = 1.8V/2.5V +70 C; unless noted, bold values indicate –40 C ...

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... KS8995M Symbol Parameter 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Output Jitters 10BaseTX Receive V Squelch Threshold SQ 10BaseT Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/Fall Times M9999-120403 Condition ...

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... KS8995M Timing Diagrams Receive Timing SCL SDA Figure 12. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 13. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 t Output Valid OV1 December 2003 ...

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... KS8995M Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-120403 ts2 tcyc2 th2 Figure 14. SNI Input Timing tcyc2 tov2 Figure 15. SNI Output Timing Table 18. SNI Timing Parameters ...

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... KS8995M Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 16. MAC Mode MII Timing – Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 17. MAC Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BaseT) CYC3 t Clock Cycle (10BaseT) ...

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... KS8995M Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 18. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 19. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BaseT) CYC4 t Clock Cycle (10BaseT) ...

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... KS8995M SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect Time SHSL t Data Input Set-Up Time DVCH ...

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... KS8995M SPIS_N SPIC tCLQX SPIQ SPID Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ Fall Time QHQL t SPIQ Disable Time SHQZ M9999-120403 ...

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... KS8995M Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC December 2003 tsr tcs tch trc Figure 22. Reset Timing Table 23. Reset Timing Parameters ...

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... KS8995M Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max ...

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... KS8995M Package Information MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...

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