KS8893MQL Micrel Inc, KS8893MQL Datasheet - Page 71

• Manufacturer Part Number: KS8893MQL
• Description: IC MANAGED SWITCH 10/100 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8893MQL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1457

Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Note: Bits [2:0] are used for spanning tree support.
Bit
7
6
5
4
3
2
1
0
December 2007
Name
Reserved
Ingress VLAN
Filtering
Discard non
PVID Packets
Force Flow
Control
Back Pressure
Enable
Transmit
Enable
Receive
Enable
Learning
Disable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Do not change the default value.
= 1, the switch will discard packets whose VID
port membership in VLAN table bits [18:16] does
not include the ingress port.
= 0, no ingress VLAN filtering.
= 1, the switch will discard packets whose VID
does not match ingress port default VID.
= 0, no packets will be discarded
= 1, will always enable full duplex flow control on
the port, regardless of AN result.
= 0, full duplex flow control is enabled based on
AN result.
= 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure
= 1, enable packet transmission on the port
= 0, disable packet transmission on the port
= 1, enable packet reception on the port
= 0, disable packet reception on the port
= 1, disable switch address learning capability
= 0, enable switch address learning
71
Default
0
0
0
Pin value during
reset:
For port 1,
P1FFC pin
For port 2,
P2FFC pin
For port 3, this
bit has no
meaning. Flow
control is set by
Reg. 6, bit 5.
0
1
1
0
M9999-121007-1.5