KS8842-32MQL Micrel Inc, KS8842-32MQL Datasheet - Page 19

• Manufacturer Part Number: KS8842-32MQL
• Description: IC SWITCH 10/100 32BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8842-32MQL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KS8842-PMQL-EVAL - EVAL KIT EXPERIMENTAL KS8842KS8842-16MQL-EVAL - EVAL KIT EXPERIMENTAL KS8842
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant
• Other names: 576-1459

Micrel, Inc.
October 2007
Ball Number
B8
C8
A7
B7
C7
A6
B6
C6
A5
B5
A4
B4
A3
B3
Ball Name
CYCLEN
VLBUSN
P2LED3
P1LED3
SRDYN
LDEVN
INTRN
EEDO
EECS
ARDY
EEEN
EESK
EEDI
RDN
Type
Opu
Opd
Opd
Opu
Opd
Opd
Opd
Opd
Opd
Ipd
Ipd
Ipd
Ipd
Ipd
Ball Function
This ball should be tied Low or unconnected if it is in asynchronous mode.
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8842M drives this ball low to
signal wait states.
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8842M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
Read Strobe Not
Asynchronous read strobe, active Low.
EEPROM Chip Select
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock. This ball needs an
external 4.7K pull-up resistor.
Cycle Not
For VLBus-like mode cycle signal; this ball follows the addressing cycle to signal
the command cycle.
For burst mode (32-bit interface only), this ball stays High for read cycles and
Low for write cycles.
Port 2 LED indicator
See the description in balls A9, B9, and C9.
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or
EISA-like burst mode.
EEPROM Enable
EEPROM is enabled and connected when this ball is pull-up.
EEPROM is disabled when this ball is pull-down or no connect.
Port 1 LED indicator
See the description in balls A10, B10, and C10.
EEPROM Data Out
This ball is connected to DI input of the serial EEPROM.
EEPROM Serial Clock
A 4
on-chip bus speed @ 125 MHz) serial output clock cycle to load configuration
data from the serial EEPROM.
EEPROM Data In
This ball is connected to DO output of the serial EEPROM when EEEN is pull-
up.
µ
s (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns (OBCR[1:0]=00
19
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9