SI8400AB-B-IS Silicon Laboratories Inc, SI8400AB-B-IS Datasheet - Page 13

• Manufacturer Part Number: SI8400AB-B-IS
• Description: IC ISOLATOR BIDIR I2C 8-SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI8400AB-B-IS

• Number Of Channels: 4
• Package / Case: 8-SOIC (3.9mm Width)
• Inputs - Side 1/side 2: 2/2
• Isolation Rating: 2500Vrms
• Voltage - Supply: 3 V ~ 5.5 V
• Data Rate: 10Mbps
• Output Type: Open Drain
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: SMD/SMT
• Propagation Delay Time: 20 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4.2 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Surface Mount
• Package Type: SOIC W
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1765 - KIT EVAL FOR SI84XXISO
• Propagation Delay: -
• Lead Free Status / Rohs Status: Compliant

3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own under
voltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally
enters UVLO when AVDD falls below AVDD
operates the same as Side A with respect to its BVDD supply.
BVDD
INPUT
OUTPUT
AVDD
UVLO+
UVLO-
UVLO+
UVLO-
tSTART
tSD
Figure 7. Device Behavior during Normal Operation
tSTART
UVLO–
and exits UVLO when AVDD rises above AVDD
tSTART
Rev. 1.3
tPHL
tPLH
Si840x
UVLO+
. Side B
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