SI8455BB-A-IS1 Silicon Laboratories Inc, SI8455BB-A-IS1 Datasheet
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SI8455BB-A-IS1
Specifications of SI8455BB-A-IS1
Related parts for SI8455BB-A-IS1
SI8455BB-A-IS1 Summary of contents
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... IEC 60950, 61010 approved Description Silicon Lab's family of ultra low power digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These devices are available in 16-pin wide-body and narrow-body SOIC packages. ...
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Si8450/51/52/55 2 Rev. 1.2 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si8450/51/52/55 1. Electrical Specifications Table 1. Electrical Characteristics ( V±10 V±10%, T DD1 DD2 A Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage ...
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Table 1. Electrical Characteristics (Continued V±10 V±10%, T DD1 DD2 A Parameter Symbol 10 Mbps Supply Current (All inputs = 5 MHz square wave all outputs) Si8450Bx, Si8455Bx V ...
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Si8450/51/52/55 Table 1. Electrical Characteristics (Continued V±10 V±10%, T DD1 DD2 A Parameter Symbol Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay t PHL Pulse Width Distortion | PLH PHL ...
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V Typical Input t PLH 90% 90% 1.4 V 10% 10% Typical Output t r Figure 2. Propagation Delay Timing Si8450/51/52/55 t PHL t f Rev. 1.2 7 ...
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Si8450/51/52/55 Table 2. Electrical Characteristics (V = 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 Output Impedance Enable ...
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Table 2. Electrical Characteristics (Continued 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter 10 Mbps Supply Current (All inputs = 5 MHz square wave all outputs) Si8450Bx, Si8455Bx V DD1 V ...
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Si8450/51/52/55 Table 2. Electrical Characteristics (Continued 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion | PLH PHL 2 Propagation Delay Skew ...
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Table 3. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter High Level Input Voltage Low Level Input Voltage High Level Output ...
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Si8450/51/52/55 Table 3. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter 10 Mbps Supply Current (All inputs = 5 MHz square ...
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Table 3. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width ...
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Si8450/51/52/55 Table 4. Absolute Maximum Ratings Parameter 2 Storage Temperature Ambient Temperature Under Bias 3 Supply Voltage (Revision A) 3 Supply Voltage (Revision B) Input Voltage Output Voltage Output Current Drive Channel Lead Solder Temperature (10 s) Maximum Isolation Voltage ...
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Table 7. Insulation and Safety-Related Specifications Parameter 1 Nominal Air Gap (Clearance) Nominal External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) 2 Resistance (Input-Output) 2 Capacitance (Input-Output) 3 Input Capacitance Notes: 1. The values in ...
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Si8450/51/52/55 Table 9. IEC 60747-5-2 Insulation Characteristics for Si845xxB* Parameter Maximum Working Insulation Voltage Input to Output Test Voltage Highest Allowable Overvoltage (Transient Overvoltage sec) TR Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at T ...
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Table 11. Thermal Characteristics Parameter Symbol IC Junction-to-Air Thermal JA Resistance 500 400 300 200 100 0 Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 500 400 300 ...
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Si8450/51/52/55 Table 12. Si845x Logic Operation Table V EN VDDI I 1,2,3,4 1,5,6 1,2 Input State Input ...
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P/N 1,2 1,2 EN1 EN2 Si8450 — H Outputs B1, B2, B3, B4, B5 are enabled and follow input state. — L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state. Si8451 H ...
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Si8450/51/52/55 2. Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 1, 2, and 3 for actual specification limits ...
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Falling Edge -40 - Temperature (Degrees C) Figure 11. Propagation Delay vs. Temperature Rising Edge 80 100 120 Rev. 1.2 Si8450/51/52/55 21 ...
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Si8450/51/52/55 3. Application Information 3.1. Theory of Operation The operation of an Si845x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path ...
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Eye Diagram Figure 14 illustrates an eye-diagram taken on an Si8450. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8450 ...
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Si8450/51/52/55 3.3. Layout Recommendations Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100–240 ...
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RF Radiated Emissions The Si845x family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but ...
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... Power Supply Bypass Capacitors (Revision A Only) When using the ISOpro isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V supply). Although rise time is power supply dependent, > ...
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Pin Descriptions (Si8450/51/52) Narrow Body SOIC 1 V DD1 EN1/NC 8 GND1 Top View (Si8450/51/52) Name SOIC-16 Pin DD1 ...
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Si8450/51/52/55 6. Pin Descriptions (Si8455) Narrow Body SOIC 1 V DD1 2 GND1 GND1 Top View (Si8455) Name SOIC-16 Pin DD1 GND1 ...
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... Si8452AB-B-IS1 3 Si8452BB-B-IS1 3 Si8455BB-B-IS1 5 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs. ...
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... Si8452BB-A-IS1 3 2 Si8455BB-A-IS1 5 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs. ...
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Package Outline: 16-Pin Wide Body SOIC Figure 18 illustrates the package details for the Si845x Digital Isolator. Table 17 lists the values for the dimensions shown in the illustration. Table 17. Package Diagram Dimensions Figure 18. 16-Pin Wide Body ...
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Si8450/51/52/55 9. Landing Pattern: 16-Pin Wide-Body SOIC Figure 19 illustrates the recommended landing pattern details for the Si845x in a 16-pin wide-body SOIC. Table 18 lists the values for the dimensions shown in the illustration. Table 18. 16-Pin Wide Body ...
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Package Outline: 16-Pin Narrow Body SOIC Figure 20 illustrates the package details for the Si845x in a 16-pin narrow-body SOIC (SO-16). Table 19 lists the values for the dimensions shown in the illustration. Figure 20. 16-pin Small Outline Integrated ...
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Si8450/51/52/55 Table 19. Package Diagram Dimensions (Continued) h θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid ...
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Landing Pattern: 16-Pin Narrow Body SOIC Figure 21 illustrates the recommended landing pattern details for the Si845x in a 16-pin narrow-body SOIC. Table 20 lists the values for the dimensions shown in the illustration. Figure 21. 16-Pin Narrow Body ...
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Si8450/51/52/55 12. Top Marking: 16-Pin Wide Body SOIC Figure 22. Si8450/51/52/55 Top Marking Line 1 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Line 2 Marking Year WW = Workweek TTTTTT = Mfg Code ...
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Top Marking: 16-Pin Narrow Body SOIC Figure 23. 16-Pin Narrow Body SOIC Top Marking Table 22. 16-Pin Narrow Body SOIC Top Marking Table Base Part Number Ordering Options Line 1 Marking: (See Ordering Guide for more information). Circle = ...
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Si8450/51/52/ OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated all specs to reflect latest silicon. Added "4. Errata and Design Migration Guidelines (Revision A Only)" on page 26. Added "13. Top Marking: 16-Pin ...
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N : OTES Si8450/51/52/55 Rev. 1.2 39 ...
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