HCPL-543K#200 Avago Technologies US Inc., HCPL-543K#200 Datasheet
HCPL-543K#200
Specifications of HCPL-543K#200
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HCPL-543K#200 Summary of contents
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... Hermetically Sealed, Very High Speed, Logic Gate Optocouplers Data Sheet HCPL-540X,* 5962-89570, HCPL-543X, HCPL-643X, 5962-89571 *See matrix for available extensions. Description These units are single and dual channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature ...
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... Pad LCCC Surface Mount 2 None HCPL-6430 HCPL-6431 HCPL-643K Solder Pads* 5962- 89571022X 89571022A 5962- 8957104K2X 8957104K2A ...
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Functional Diagrams 8 Pin DIP Through Hole 1 Channel GND Note: All DIP devices have common V ground connections. Outline Drawings 20 Terminal LCCC Surface Mount, 2 Channels 8.70 (0.342) ...
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Leaded Device Marking Avago DESIGNATOR A QYYWWZ Avago P/N XXXXXX XXXXXXX DSCC SMD* DSCC SMD* XXX XXX • PIN ONE/ 50434 ESD IDENT * QUALIFIED PARTS ONLY Hermetic Optocoupler Options ;; ;; ; ; ; Option Description 100 Surface mountable ...
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... CATHODE Note enable pin 7. An external 0. 0.1 F bypass capacitor must be connected between V and ground for each package type. CC ESD Classification (MIL-STD-883, Method 3015) HCPL-5400/01/0K HCPL-5430/31/3K and HCPL-6430/31/3K Recommended Operating Conditions Parameter Symbol Input Current (High) I F(ON) Supply Voltage, Output V CC ...
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Electrical Characteristics +125 unless otherwise specified. Parameter Sym. Low Level Output Voltage High Level Output Voltage Output Leakage ...
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Typical Characteristics All typical values are Parameter Input Current Hysteresis Input Diode Temperature Coefficient Resistance (Input-Output) Capacitance (Input-Output) Logic Low Short Circuit Output Current Logic High Short Circuit Output Current Output Rise Time ...
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... The HCPL-6430, HCPL-6431, and HCPL-643K dual channel parts function as two independent single channel units. Use the single channel parameter limits. ...
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PULSE GEN 500 kHz 25 % DUTY CYCLE D.U. INPUT MONITORING NODE 100 GND THE PROBE AND JIG CAPACITANCES ARE REPRESENTED BY C ...
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Figure 9. Typical enable propagation delay vs. ambient temperature. (single channel product only D.U. 0.1 µ – GND – PULSE GEN. Figure 11. Test diagram for ...
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... IN 274 A GND 1 TOTEM POLE OUTPUT GATE (e.g. 54AS1000) Figure 13. Recommended HCPL-5400 interface circuit 11 given a stimulus at the input. Propagation delay from high to low (t for a system’s output to change from a Logic Logic 0, when given a stimulus at the input (see Figure 5). When t and t PLH results. Pulse width distortion is defined as |t and determines the maximum data rate capability of a distortion-limited system ...
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... IN A GND 1 1 Figure 16. Alternative HCPL-5430 and HCPL-6430 interface circuit For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5968-0405E ...