DS1990R-F3# Maxim Integrated Products, DS1990R-F3# Datasheet - Page 4

• Manufacturer Part Number: DS1990R-F3#
• Description: IBUTTON SERIAL NUMBER F3
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1990R-F3#

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 8B
• Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Number iButton
Each DS1990R contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a CRC of the first 56 bits. See Figure 2 for details.
The 1-Wire CRC is generated using a polynomial gen-
erator consisting of a shift register and XOR gates as
shown in Figure 3. The polynomial is X
Additional information about the 1-Wire Cyclic
Redundancy Check (CRC) is available in Application
Note 27: Understanding and Using Cyclic Redundancy
Checks with Maxim iButton Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of CRC returns the shift register to all 0s.
Figure 2. 64-Bit Lasered ROM
Figure 3. 1-Wire CRC Generator
4
_______________________________________________________________________________________
X
0
MSB
MSB
STAGE
1ST
CRC CODE
X
1
8-BIT
STAGE
2ND
LSB
X
2
MSB
STAGE
64-Bit Lasered ROM
3RD
X
3
8
STAGE
4TH
+ X
5
+ X
POLYNOMIAL = X
4
48-BIT SERIAL NUMBER
+ 1.
X
4
8
+ X
5
STAGE
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS1990R
is a slave device. The bus master is typically a micro-
controller or PC. For small configurations, the 1-Wire
communication signals can be generated under soft-
ware control using a single port pin. Alternatively, the
DS2480B 1-Wire line driver chip or serial-port adapters
based on this chip (DS9097U series) can be used. This
simplifies the hardware design and frees the micro-
processor from responding in real time. The discussion
of this bus system is broken down into three topics:
hardware configuration, transaction sequence, and
1-Wire signaling (signal types and timing). The 1-Wire
protocol defines bus transactions in terms of the bus
state during specific time slots that are initiated on the
falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of
the Application Note 937: Book of iButton Standards .
5TH
+ X
4
+ 1
X
5
STAGE
6TH
LSB
1-Wire Bus System
X
6
MSB
STAGE
7TH
8-BIT FAMILY CODE
(01h)
X
INPUT DATA
7
STAGE
8TH
LSB
LSB
X
8