DS1977-F5# Maxim Integrated Products, DS1977-F5# Datasheet - Page 3

• Manufacturer Part Number: DS1977-F5#
• Description: IBUTTON EEPROM 32KBit F5
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1977-F5#

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 32KB
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
Presence Detect
Sample Time
I/O Pin, 1-Wire Write
Write-0 Low Time
Write-1 Low Time
I/O Pin, 1-Wire Read
Read Low Time
Read Sample Time
I/O Pin, Strong Pullup
Strong Pullup Read
Strong Pullup Write
Strong Pullup password
verification
EEPROM
Programming Current
Write/Erase Cycles
Data Retention
t
t
t
t
t
SLOT
RSTL
PDH
PDL
W0L
Parameter
PARAMETER
(incl. t
Name
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the data pin could be 5nF when power is first applied.
V
maximum specifications are valid at V
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%
of V
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
duration for the master to pull the line low is t
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
the bus master. The actual maximum duration for the master to pull the line low is t
TL
REC
and V
PUP
)
TH
and the time at which the voltage is 10% of V
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
TH
are functions of the internal supply voltage, which is a function of V
61µs
480µs
15µs
60µs
60µs
Standard Speed
min
SYMBOL
N
I
t
t
t
LPROG
t
t
t
t
SPUW
SPUR
SPUV
t
CYCLE
MSR
MSP
W0L
W1L
t
RET
RL
(undef.)
(undef.)
60µs
240µs
120µs
Standard Values
max
Standard speed, V
(Note 1)
Standard speed (Note 1)
Overdrive speed (Note 1)
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
Standard speed,
V
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
(Note 1)
(Note 1)
(Note 1)
PUPMAX
PUP
7µs
48µs
2µs
8µs
6µs
> 4.5V (Notes 1, 14)
(5.25V). In any case, V
W1LMAX
Overdrive Speed
min
CONDITIONS
ILMAX
+ t
PUP
whenever the master drives the line low.
F
3 of 29
.
- ε and t
REH
(undef.)
80µs
6µs
24µs
16µs
PUP
after V
max
W0LMAX
> 4.5V
TL
TH
< V
+ t
has been reached before.
F
TH
65µs
480µs
15µs
60µs
60µs
- ε respectively.
Standard Speed
< V
min
PUP
PUP
1)
t
t
t
22.46
RL
RL
RL
100k
2.64
0.62
MIN
.
7.5
and the 1-Wire recovery times. The V
65
68
60
10
RLMAX
HY
6
5
1
5
1
+ δ
+ δ
+ δ
to be detected as logic '0'.
(undef.)
640µs
60µs
240µs
120µs
+ t
F
DS1977 Values
max
.
TYP
IL
IL
to V
to the input-high threshold of
8µs
48µs
2.5µs
8µs
6µs
Overdrive Speed
min
TH
1)
15 - δ
. The actual maximum
MAX
10.5
2 - δ
120
75
75
16
15
20
15
2
2
7
(undef.)
80µs
6.5µs
24µs
16µs
TH
UNITS
max
DS1977
years
mA
and V
ms
ms
ms
µs
µs
µs
µs
µs
—
TL