SDCFJ-1024-388 SanDisk, SDCFJ-1024-388 Datasheet - Page 49

• Manufacturer Part Number: SDCFJ-1024-388
• Description: COMPACT FLASH 1GB
• Manufacturer: SanDisk
• Type: CompactFlashr

Specifications of SDCFJ-1024-388

• Memory Size: 1GB
• Memory Type: CompactFLASH
• Density: 1GByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 50
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.135/4.5V
• Operating Supply Voltage (max): 3.465/5.5V
• Programmable: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ATA Drive Register Set Definition and Protocol
4.4. True IDE Mode Addressing
When the CompactFlash Memory Card is configured in the True IDE Mode the I/O decoding is as listed in
Table 4-5.
4.5. ATA Registers
NOTE: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset
4.5.1. Data Register (Address—1F0[170];Offset 0, 8, 9)
The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash Memory Card
data buffer and the Host. This register overlaps the Error Register. The table below describes the combinations of
data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature
Register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the
PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles.
NOTE: Because of the overlapped registers, access to the 1F1, 171 or offset 1 are not defined for word (-CE2 = 0
4-4
address may be accessed at its normal address and also the corresponding even address (normal address -1)
using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16 is high (not asserted) and
an I/O cycle is being performed.
and -CE1 = 0) operations. SanDisk products treat these accesses as accesses to the Word Data Register. The
duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed by
the socket.
-CE2
1
1
1
1
1
1
1
1
0
0
-CE1
0
0
0
0
0
0
0
0
1
1
Table 4-5. True IDE Mode I/O Decoding
CompactFlash
A2
0
0
0
0
1
1
1
1
1
1
A1
0
0
1
1
0
0
1
1
1
1
®
Memory Card Product Manual, Rev. 11.0 ©2006 SanDisk Corporation
A0
0
1
0
1
0
1
0
1
0
1
Even RD Data
Error Register
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Alt Status
Drive Address
-IORD=0
Even WR Data
Features
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Command
Device Control
Reserved
-IOWR=0