SDCFJ-2048-388 SanDisk, SDCFJ-2048-388 Datasheet - Page 51
![COMPACT FLASH 2GB](/photos/7/83/78343/mfg_sdcfj_series_sml.jpg)
SDCFJ-2048-388
Manufacturer Part Number
SDCFJ-2048-388
Description
COMPACT FLASH 2GB
Manufacturer
SanDisk
Datasheet
1.SDCFH-1024-388.pdf
(108 pages)
Specifications of SDCFJ-2048-388
Memory Size
2GB
Memory Type
CompactFLASH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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© 2007 SanDisk Corporation
SanDisk CompactFlash Card OEM Product Manual
4.5.9
4.5.10
Status & Alternate Status Registers (Address–1F7[177]&3F6[376]; Offsets 7 &
Eh)
These registers return the card status when read by the host. Reading the Status Register clears
a pending interrupt while reading the Auxiliary Status Register does not. The meaning of the
status bits are described as follows:
Device Control Register (Address–3F6[376]; Offset Eh)
This register is used to control the CompactFlash Memory Card interrupt request and to issue
an ATA soft reset to the card. The bits are defined as follows:
BUSY
Bit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D7
X
CORR
Name
BUSY
DWF
DRQ
RDY
DSC
ERR
RDY
0
D6
D6
X
Set when the CompactFlash Card has access to the command buffer and
registers and the host is locked out from accessing the command register
and buffer. No other bits in this register are valid when this bit is set to a 1.
RDY indicates whether the device is capable of performing card operations.
This bit is cleared at power-up and remains cleared until card is ready to
accept a command.
If set, indicates a write fault has occurred.
Set when the card is ready.
Set when the card requires that information be transferred either to or from
the host through the Data Register.
Set when a correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read
operation.
Always set to 0.
Set when the previous command has ended in some type of error. The bits
in the Error Register contain additional information describing the error.
DWF
D5
D5
X
DSC
D4
D4
X
4-7
DRQ
D3
D3
1
Description
SW Rst
CORR
D2
D2
ATA Register Set and Protocol
-IEn
D1
D1
0
Rev. 12.0, 02/07
ERR
D0
D0
0
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