HDSP-2111-GH000 Avago Technologies US Inc., HDSP-2111-GH000 Datasheet - Page 13
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HDSP-2111-GH000
Manufacturer Part Number
HDSP-2111-GH000
Description
DISPLAY 5X7 8CHAR .2" YELLOW
Manufacturer
Avago Technologies US Inc.
Series
HDSP-211xr
Datasheet
1.HDSP-2113.pdf
(16 pages)
Specifications of HDSP-2111-GH000
Package / Case
28-DIP
Color
Yellow
Size / Dimension
1.68" x 0.77" (42.59mm x 19.58mm)
Display Type
Alphanumeric
Number Of Digits/alpha
8
Digit/alpha Size
0.20" (5mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Common Pin
-
Control Word Register
Figure 6 shows how to access the Control Word Register.
This 8-bit register performs five functions: Bright ness
control, Flash RAM control, Blinking, Self Test, and Clear.
Each function is independent of the others; how ever, all
bits are updated during each Control Word write cycle.
Brightness (Bits 0-2)
Bits 0-2 of the Control Word adjust the brightness of the
display. Bits 0-2 are interpreted as a three bit binary code
with code (000) corresponding to maximum brightness
and code (111) corresponding to a blanked display. In
addition to varying the display brightness, bits 0-2 also
vary the average value of I
bright ness level by multiplying the percent brightness
level by the value of I
These values of I
Flash Function (Bit 3)
Bit 3 determines whether the flashing character attribute
is on or off. When bit 3 is a“1, ” the output of the Flash RAM
is checked. If the content of a loca tion in the Flash RAM is
a “1, ” the associated digit will flash at approximately 2 Hz.
For an external clock, the blink rate can be calculated by
driving the clock frequency by 28,672. If the flash enable
bit of the Control Word is a “0, ” the content of the Flash
RAM is ignored. To use this function with multiple dis play
systems, see the Display Reset section.
Blink Function (Bit 4)
Bit 4 of the Control Word is used to synchronize blinking
of all eight digits of the display. When this bit is a “1” all
eight digits of the display will blink at approx i mately 2
Hz. The actual rate is dependent on the clock fre quency.
For an external clock, the blink rate can be calculated by
dividing the clock frequency by 28,672. This func tion will
override the Flash function when it is active. To use this
function with multiple display systems, see the Display
Reset section.
Table 2. Current Requirements at Different Brightness Levels V
Symbol
I
13
DD
(V)
D
0
0
0
0
1
1
1
2
DD
are shown in Table 2.
D
0
0
1
1
0
0
1
1
DD
DD
at the 100% bright ness level.
. I
D
0
1
0
1
0
1
0
0
DD
can be calcu lated at any
%
Brightness
100
80
53
40
27
20
13
DD
Current at 25°C
Typ.
200
160
106
80
54
40
26
= 5.0 V
CONTROL SIGNALS
FLASH RAM ADDRESS
FLASH RAM DATA FORMAT
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 5. Logic levels to access the flash RAM.
CONTROL SIGNALS
CONTROL WORD ADDRESS
Figure 6. Logic levels to access the control word register
RST
RST
D
FL
D
1
0
X
FL
0 NORMAL OPERATION
1 CLEAR FLASH AND CHARACTER RAMS
CONTROL WORD DATA FORMAT
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
1
1
C
7
7
CE
A
D
X
X
CE
0
A
D
S
0
1
0
1
4
6
4
6
WR
A
D
WR
0
0
1
1
X
X
Units
mA
mA
mA
mA
mA
mA
mA
A
D
S
X NORMAL OPERATION; X IS IGNORED
X START SELF TEST; RESULT GIVEN IN X
0
0
1
1
0
3
5
3
5
X = 0 FAILED
RD
A
D
0
1
0
1
X
RD
BL
A
D
0
1
0
1
2
4
X
0 DISABLE BLINKING
1 ENABLE BLINKING
CHARACTER
2
4
ADDRESS
UNDEFINED
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
A
UNDEFINED
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
D
X
A
D
1
3
X
F
0 DISABLE FLASH
1 ENABLE FLASH
1
3
A
X = 1 PASSED
D
X
0
2
A
D
B
X
0
0
0
0
1
1
1
1
0
2
000 = LEFT MOST
111 = RIGHT MOST
D
X
1
D
B
0
0
1
1
0
0
1
1
1
D
0
1
0
D
B
0
1
0
1
0
1
0
1
0
REMOVE FLASH AT
SPECIFIED DIGIT LOCATION
STORE FLASH AT
SPECIFIED DIGIT LOCATION
100%
80%
53%
40%
27%
20%
13%
0%
BRIGHTNESS
CONTROL
LEVELS