SCDV5541 OSRAM Opto Semiconductors Inc, SCDV5541 Datasheet - Page 12

• Manufacturer Part Number: SCDV5541
• Description: DISPLAY 4CHAR .123" 5X5 YLW DIP
• Manufacturer: OSRAM Opto Semiconductors Inc
• Series: Intelligent Display®r

Specifications of SCDV5541

• Millicandela Rating: 5.4mcd
• Size / Dimension: 0.78" L x 0.40" W x 0.20" H (19.91mm x 10.16mm x 5.08mm)
• Color: Yellow
• Configuration: 5 x 5
• Number Of Digits: 4
• Character Size: 0.123 in
• Illumination Color: Yellow
• Wavelength: 583 nm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Luminous Intensity: 5.4 mcd
• Viewing Area (w X H): 2.41 mm x 3.41 mm
• Display Type: 5 x 7 Dot Matrix
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Forward (vf) Typ: -
• Internal Connection: -
• Lead Free Status / Rohs Status: Details
• Other names: Q68000A8891

Microprocessor Interface
The microprocessor interface is through the serial port, SPI port or
one out of eight data bits on the eight bit parallel port and also con-
trol lines SDCLK and LOAD.
Power Up Sequence
Upon power up display will come on at random. Thus the display
should be reset at power-up. The reset will set the Address Regis-
ter to Digit 0, User RAM is set to 0 (display blank) the Control Word
is set to 0 (100% brightness with Lamp Test off) and the internal
counters are reset.
SCDV554X Interface with Motorola 68HC05C4 Microprocessor (using SPI port)
Cascading Multiple Displays
2006-01-23
RST
DATA
SDCLK
A0
A1
A2
A3
LD
V
CC
Decoder
Address
DATA
RST
Chip
CE
38
39
20
Intelligent Display
1
9
0
15
SCDV5540, SCDV5541, SCDV5542, SCDV5543, SCDV5544
68HC05C4
OSC1
OSC2
RST
PA2
CLK I/O
SDCLK
U1
V
Address Decode 1-14
CC
40
SCLK
MOSI
CLK SEL
PA0
PA1
LOAD
V
CC
11
10
33
32
14 more displays
in between
12
Cascading Multiple Displays
Multiple displays can be cascaded using the CLKSEL and CLK I/O
pins as shown below. The display designated as the Master Clock
source should have its CLKSEL pin tied high and the slaves should
have their CLKSEL pins tied low. All CLK I/O pins should be tied
together. One display CLK I/O can drive 15 slave CLK I/Os. Use
RST to synchronize all display counters.
1
2
6
7
SDCLK
LD
RST
GND
ID
DATA
CLK I/O
RST
DATA
GND
V
V
V
CS
Intelligent Display
CC
CC
CC
14
13
12
11
10
9
8
CLK I/O
SDCLK
V
CC
0.01 µF
22 µF
IDCD5232
CLK SEL
TAN
LOAD
IDCD5030